From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756366AbdLTTC6 (ORCPT ); Wed, 20 Dec 2017 14:02:58 -0500 Received: from mx1.redhat.com ([209.132.183.28]:40196 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756124AbdLTTCw (ORCPT ); Wed, 20 Dec 2017 14:02:52 -0500 Date: Wed, 20 Dec 2017 12:02:51 -0700 From: Alex Williamson To: Gary R Hook Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices Message-ID: <20171220120251.435ed475@t450s.home> In-Reply-To: <151372174181.127118.3644062052273990281.stgit@sosxen2.amd.com> References: <151372174181.127118.3644062052273990281.stgit@sosxen2.amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Wed, 20 Dec 2017 19:02:52 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 19 Dec 2017 16:15:41 -0600 Gary R Hook wrote: > The AMD IOMMU specification Rev 3.00 (December 2016) introduces a > new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register > offset 0030h (IOMMU Extended Feature Register). > > When EPHSup=1, the IOMMU hardware requires the PPR bit of the > device table entry (DTE) to be set in order to support PPR for a > particular endpoint device. > > Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for > this revision of the AMD IOMMU specification. > > Signed-off-by: Gary R Hook > --- > 0 files changed Hmm, something funky there, but looks fine otherwise. Applied to v4.16-iommu/amd. Thanks, Alex