From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752403AbdLYLt0 (ORCPT ); Mon, 25 Dec 2017 06:49:26 -0500 Received: from regular1.263xmail.com ([211.150.99.139]:59855 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752027AbdLYLtY (ORCPT ); Mon, 25 Dec 2017 06:49:24 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: jeffy.chen@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: jeffy.chen@rock-chips.com X-UNIQUE-TAG: <1c9439a6e52a3ede7e57fa5572a78a38> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Jeffy Chen To: linux-kernel@vger.kernel.org, bhelgaas@google.com Cc: linux-pm@vger.kernel.org, tony@atomide.com, shawn.lin@rock-chips.com, briannorris@chromium.org, rjw@rjwysocki.net, dianders@chromium.org, Jeffy Chen , devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Rob Herring , Mark Rutland Subject: [RFC PATCH v11 1/5] dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq Date: Mon, 25 Dec 2017 19:47:38 +0800 Message-Id: <20171225114742.18920-2-jeffy.chen@rock-chips.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171225114742.18920-1-jeffy.chen@rock-chips.com> References: <20171225114742.18920-1-jeffy.chen@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We are going to handle PCIe WAKE# pin for PCI devices in the pci core, so add definitions of the optional PCIe WAKE# pin for PCI devices. Also add an definition of the optional PCI interrupt pin for PCI devices to distinguish it from the PCIe WAKE# pin. Signed-off-by: Jeffy Chen --- Changes in v11: Only add irq definitions for PCI devices and rewrite the commit message. Changes in v10: None Changes in v9: Add section for PCI devices and rewrite the commit message. Changes in v8: Add optional "pci", and rewrite commit message. Changes in v7: None Changes in v6: None Changes in v5: Move to pci.txt Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/pci/pci.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index c77981c5dd18..3045ac452f27 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -24,3 +24,13 @@ driver implementation may support the following properties: unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. + +PCI devices may support the following properties: + +- interrupts: Interrupt specifier for each name in interrupt-names. +- interrupt-names: + May contain "wakeup" for PCIe WAKE# interrupt and "pci" for PCI interrupt. + The PCI devices may optionally include an 'interrupts' property that + represents the legacy PCI interrupt. And when we try to specify the PCIe + WAKE# pin, a corresponding 'interrupt-names' property is required to + distinguish them. -- 2.11.0