From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751853AbeAEJ4c (ORCPT + 1 other); Fri, 5 Jan 2018 04:56:32 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:38215 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751655AbeAEJ4a (ORCPT ); Fri, 5 Jan 2018 04:56:30 -0500 From: Yixun Lan To: Kevin Hilman , CC: Neil Armstrong , Jerome Brunet , Rob Herring , Mark Rutland , Carlo Caione , Yixun Lan , , , Subject: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description Date: Fri, 5 Jan 2018 17:56:19 +0800 Message-ID: <20180105095621.196472-5-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180105095621.196472-1-yixun.lan@amlogic.com> References: <20180105095621.196472-1-yixun.lan@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.20.164] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Describe the pinctrl info for the UART controller which found in the Meson-AXG SoCs. Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f6bf01cfff4b..78bb206e2897 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -303,6 +303,70 @@ function = "pwm_d"; }; }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_a_cts_rts_pins: uart_a_cts_rts { + mux { + groups = "uart_ctx_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + uart_b_x_pins: uart_b_x { + mux { + groups = "uart_tx_b_x", + "uart_rx_b_x"; + function = "uart_b"; + }; + }; + + uart_b_x_cts_rts_pins: uart_b_x_cts_rts { + mux { + groups = "uart_cts_b_x", + "uart_rts_b_x"; + function = "uart_b"; + }; + }; + + uart_b_z_pins: uart_b_z { + mux { + groups = "uart_tx_b_z", + "uart_rx_b_z"; + function = "uart_b"; + }; + }; + + uart_b_z_cts_rts_pins: uart_b_z_cts_rts { + mux { + groups = "uart_cts_b_z", + "uart_rts_b_z"; + function = "uart_b"; + }; + }; + + uart_ao_b_z_pins: uart_ao_b_z { + mux { + groups = "uart_ao_tx_b_z", + "uart_ao_rx_b_z"; + function = "uart_ao_b_groupz"; + }; + }; + + uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { + mux { + groups = "uart_ao_cts_b_z", + "uart_ao_rts_b_z"; + function = "uart_ao_b_groupz"; + }; + }; }; }; @@ -346,6 +410,38 @@ #gpio-cells = <2>; gpio-ranges = <&pinctrl_aobus 0 0 15>; }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_ao_tx_a", + "uart_ao_rx_a"; + function = "uart_ao_a"; + }; + }; + + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { + mux { + groups = "uart_ao_cts_a", + "uart_ao_rts_a"; + function = "uart_ao_a"; + }; + }; + + uart_ao_b_pins: uart_ao_b { + mux { + groups = "uart_ao_tx_b", + "uart_ao_rx_b"; + function = "uart_ao_b"; + }; + }; + + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { + mux { + groups = "uart_ao_cts_b", + "uart_ao_rts_b"; + function = "uart_ao_b"; + }; + }; }; pwm_AO_ab: pwm@7000 { -- 2.15.1