From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752642AbeAERMC (ORCPT + 1 other); Fri, 5 Jan 2018 12:12:02 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:43838 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752330AbeAERKF (ORCPT ); Fri, 5 Jan 2018 12:10:05 -0500 X-Google-Smtp-Source: ACJfBospcfryz1/poKdTP45k3/cCXTsVp0PUB+K+HhSCJMcpM7aFgo3rKa9syBiOyqzHU4hEBDrsgw== From: Jerome Brunet To: Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org Cc: Jerome Brunet , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Vladimir Zapolskiy , Sylvain Lemieux , Andy Gross , David Brown Subject: [PATCH 1/5] clk: divider: read-only divider can propagate rate change Date: Fri, 5 Jan 2018 18:09:55 +0100 Message-Id: <20180105170959.17266-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180105170959.17266-1-jbrunet@baylibre.com> References: <20180105170959.17266-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the register shall be left un-touched, but it does not mean the clock should stop rate propagation if CLK_SET_RATE_PARENT is set This is properly handled in qcom clk-regmap-divider but it was not in the generic divider Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Signed-off-by: Jerome Brunet --- drivers/clk/clk-divider.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index b49942b9fe50..a851d3e04c7f 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -348,6 +348,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_divider *divider = to_clk_divider(hw); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); int bestdiv; /* if read only, just return current value */ @@ -356,6 +357,15 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, bestdiv &= div_mask(divider->width); bestdiv = _get_div(divider->table, bestdiv, divider->flags, divider->width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!hw_parent) + return -EINVAL; + + *prate = clk_hw_round_rate(hw_parent, rate * bestdiv); + } + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } -- 2.14.3