From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932952AbeALB2v (ORCPT + 1 other); Thu, 11 Jan 2018 20:28:51 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:57546 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932478AbeALB2e (ORCPT ); Thu, 11 Jan 2018 20:28:34 -0500 From: Chris Packham To: linux@armlinux.org.uk, bp@alien8.de, jlu@pengutronix.de Cc: Chris.Packham@alliedtelesis.co.nz, thomas.petazzoni@free-electrons.com, kernel@pengutronix.de, gregory.clement@free-electrons.com, Chris Packham , Mauro Carvalho Chehab , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 8/8] EDAC: armada_xp: Add support for more SoCs Date: Fri, 12 Jan 2018 14:27:55 +1300 Message-Id: <20180112012755.20495-9-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz> References: <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The Armada 38x and other integrated SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the Armada XP SoCs. This means that the definition of "full" and "half" width is reduced from 64/32 to 32/16. Signed-off-by: Chris Packham --- drivers/edac/armada_xp_edac.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c index 70cff01afc8d..03a18b54467a 100644 --- a/drivers/edac/armada_xp_edac.c +++ b/drivers/edac/armada_xp_edac.c @@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev) axp_mc_read_config(mci); + /* These SoCs have a reduced width bus */ + if (of_machine_is_compatible("marvell,armada380") || + of_machine_is_compatible("marvell,armadaxp-98dx3236")) + drvdata->width /= 2; + /* configure SBE threshold */ /* it seems that SBEs are not captured otherwise */ writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG); -- 2.15.1