From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965264AbeALSsG (ORCPT + 1 other); Fri, 12 Jan 2018 13:48:06 -0500 Received: from mail.skyhub.de ([5.9.137.197]:59294 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964997AbeALSsD (ORCPT ); Fri, 12 Jan 2018 13:48:03 -0500 Date: Fri, 12 Jan 2018 19:47:48 +0100 From: Borislav Petkov To: Chris Packham Cc: linux@armlinux.org.uk, jlu@pengutronix.de, thomas.petazzoni@free-electrons.com, kernel@pengutronix.de, gregory.clement@free-electrons.com, Mauro Carvalho Chehab , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 8/8] EDAC: armada_xp: Add support for more SoCs Message-ID: <20180112184748.lfzrdhuq77d73ool@pd.tnic> References: <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz> <20180112012755.20495-9-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20180112012755.20495-9-chris.packham@alliedtelesis.co.nz> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Fri, Jan 12, 2018 at 02:27:55PM +1300, Chris Packham wrote: > The Armada 38x and other integrated SoCs use a reduced pin count so the > width of the SDRAM interface is smaller than the Armada XP SoCs. This > means that the definition of "full" and "half" width is reduced from > 64/32 to 32/16. > > Signed-off-by: Chris Packham > --- > drivers/edac/armada_xp_edac.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c > index 70cff01afc8d..03a18b54467a 100644 > --- a/drivers/edac/armada_xp_edac.c > +++ b/drivers/edac/armada_xp_edac.c > @@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev) > > axp_mc_read_config(mci); > > + /* These SoCs have a reduced width bus */ > + if (of_machine_is_compatible("marvell,armada380") || > + of_machine_is_compatible("marvell,armadaxp-98dx3236")) > + drvdata->width /= 2; > + > /* configure SBE threshold */ > /* it seems that SBEs are not captured otherwise */ > writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG); > -- Reviewed-by: Borislav Petkov -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.