From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755223AbeARPAz (ORCPT ); Thu, 18 Jan 2018 10:00:55 -0500 Received: from merlin.infradead.org ([205.233.59.134]:46800 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755196AbeARO6F (ORCPT ); Thu, 18 Jan 2018 09:58:05 -0500 Message-Id: <20180118140153.375420603@infradead.org> User-Agent: quilt/0.63-1 Date: Thu, 18 Jan 2018 14:48:32 +0100 From: Peter Zijlstra From: Peter Zijlstra To: David Woodhouse , Thomas Gleixner , Josh Poimboeuf Cc: linux-kernel@vger.kernel.org, Dave Hansen , Ashok Raj , Tim Chen , Andy Lutomirski , Linus Torvalds , Greg KH , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , Dan Williams , Paolo Bonzini , Jun Nakajima , Asit Mallick , Jason Baron , Peter Zijlstra , David Woodhouse Subject: [PATCH 32/35] x86/vmx: Direct access to MSR_IA32_SPEC_CTRL References: <20180118134800.711245485@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline; filename=ashok_raj-x86_ibrs-add_direct_access_support_for_msr_ia32_spec_ctrl.patch Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ashok Raj Add direct access to MSR_IA32_SPEC_CTRL from a guest. Also save/restore IBRS values during exits and guest resume path. [peterz: rebased] Cc: Asit Mallick Cc: Arjan Van De Ven Cc: Dave Hansen Cc: Andi Kleen Cc: Andrea Arcangeli Cc: Linus Torvalds Cc: Tim Chen Cc: Thomas Gleixner Cc: Dan Williams Cc: Jun Nakajima Cc: Paolo Bonzini Cc: David Woodhouse Cc: Greg KH Cc: Andy Lutomirski Signed-off-by: Ashok Raj Signed-off-by: Peter Zijlstra (Intel) --- arch/x86/kvm/cpuid.c | 3 ++- arch/x86/kvm/vmx.c | 25 +++++++++++++++++++++++++ arch/x86/kvm/x86.c | 1 + 3 files changed, 28 insertions(+), 1 deletion(-) --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -70,6 +70,7 @@ u64 kvm_supported_xcr0(void) /* These are scattered features in cpufeatures.h. */ #define KVM_CPUID_BIT_AVX512_4VNNIW 2 #define KVM_CPUID_BIT_AVX512_4FMAPS 3 +#define KVM_CPUID_BIT_SPEC_CTRL 26 #define KF(x) bit(KVM_CPUID_BIT_##x) int kvm_update_cpuid(struct kvm_vcpu *vcpu) @@ -392,7 +393,7 @@ static inline int __do_cpuid_ent(struct /* cpuid 7.0.edx*/ const u32 kvm_cpuid_7_0_edx_x86_features = - KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS); + KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS) | KF(SPEC_CTRL); /* all calls to cpuid_count() should be made on the same cpu */ get_cpu(); --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -580,6 +580,7 @@ struct vcpu_vmx { u32 vm_entry_controls_shadow; u32 vm_exit_controls_shadow; u32 secondary_exec_control; + u64 spec_ctrl; /* * loaded_vmcs points to the VMCS currently used in this vcpu. For a @@ -3260,6 +3261,9 @@ static int vmx_get_msr(struct kvm_vcpu * case MSR_IA32_TSC: msr_info->data = guest_read_tsc(vcpu); break; + case MSR_IA32_SPEC_CTRL: + msr_info->data = to_vmx(vcpu)->spec_ctrl; + break; case MSR_IA32_SYSENTER_CS: msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); break; @@ -3367,6 +3371,9 @@ static int vmx_set_msr(struct kvm_vcpu * case MSR_IA32_TSC: kvm_write_tsc(vcpu, msr_info); break; + case MSR_IA32_SPEC_CTRL: + to_vmx(vcpu)->spec_ctrl = msr_info->data; + break; case MSR_IA32_CR_PAT: if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) @@ -6791,6 +6798,13 @@ static __init int hardware_setup(void) kvm_tsc_scaling_ratio_frac_bits = 48; } + /* + * If feature is available then setup MSR_IA32_SPEC_CTRL to be in + * passthrough mode for the guest. + */ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) + vmx_disable_intercept_for_msr(MSR_IA32_SPEC_CTRL, false); + vmx_disable_intercept_for_msr(MSR_FS_BASE, false); vmx_disable_intercept_for_msr(MSR_GS_BASE, false); vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); @@ -9299,6 +9313,15 @@ static void __noclone vmx_vcpu_run(struc vmx_arm_hv_timer(vcpu); vmx->__launched = vmx->loaded_vmcs->launched; + + /* + * Just update whatever the value was set for the MSR in guest. + * If this is unlaunched: Assume that initialized value is 0. + * IRQ's also need to be disabled. If guest value is 0, an interrupt + * could start running in unprotected mode (i.e with IBRS=0). + */ + restore_indirect_branch_speculation(vmx->spec_ctrl); + asm( /* Store host registers */ "push %%" _ASM_DX "; push %%" _ASM_BP ";" @@ -9407,6 +9430,8 @@ static void __noclone vmx_vcpu_run(struc /* Eliminate branch target predictions from guest mode */ vmexit_fill_RSB(); + vmx->spec_ctrl = stop_indirect_branch_speculation_and_save(); + /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ if (debugctlmsr) update_debugctlmsr(debugctlmsr); --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1006,6 +1006,7 @@ static u32 msrs_to_save[] = { #endif MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, + MSR_IA32_SPEC_CTRL, }; static unsigned num_msrs_to_save;