From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933278AbeARQLB (ORCPT ); Thu, 18 Jan 2018 11:11:01 -0500 Received: from mail-pg0-f44.google.com ([74.125.83.44]:34823 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933241AbeARQKy (ORCPT ); Thu, 18 Jan 2018 11:10:54 -0500 X-Google-Smtp-Source: ACJfBovVp077Wmrs7DQLdL9k2/jU6b8NhEKpD0BQkFKIzEf+4jFSBMwiD1kaLcKQDB062u1CG7yN+Q== Subject: Use arm64's scheme for registering first-level IRQ handlers on RISC-V Date: Thu, 18 Jan 2018 07:40:03 -0800 Message-Id: <20180118154005.24994-1-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 Cc: patches@groups.riscv.org From: Palmer Dabbelt To: Arnd Bergmann , Christoph Hellwig , linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch set has been sitting around for a while, but it got a bit lost in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry point for interrupt handling) to our first-level interrupt controller. While this isn't completely crazy (as the first-level interrupt controller is specified by the ISA), it is a bit awkward. This patch set decouples our trap handler from our first-level IRQ chip driver by copying what a handful of other architectures are doing. This does add an additional load to the interrupt handling path, but there's a handful of performance problems in there that I've been meaning to look at so I don't mind adding another one for now. The advantage is that our irqchip driver is decoupled from our arch port, at least at compile time.