From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755540AbeASNVv (ORCPT ); Fri, 19 Jan 2018 08:21:51 -0500 Received: from smtp2.provo.novell.com ([137.65.250.81]:46446 "EHLO smtp2.provo.novell.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755172AbeASNVm (ORCPT ); Fri, 19 Jan 2018 08:21:42 -0500 Date: Fri, 19 Jan 2018 14:21:33 +0100 From: Petr Tesarik To: Michal Hocko Cc: linux-mm@kvack.org, Andrew Morton , Vlastimil Babka , linux-kernel@vger.kernel.org, Mel Gorman , Johannes Weiner , Kemi Wang , YASUAKI ISHIMATSU , Andrey Ryabinin , Nikolay Borisov Subject: Re: [PATCH] Fix explanation of lower bits in the SPARSEMEM mem_map pointer Message-ID: <20180119142133.379d5145@ezekiel.suse.cz> In-Reply-To: <20180119123956.GZ6584@dhcp22.suse.cz> References: <20180119080908.3a662e6f@ezekiel.suse.cz> <20180119123956.GZ6584@dhcp22.suse.cz> Organization: SUSE Linux X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.31; x86_64-suse-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 19 Jan 2018 13:39:56 +0100 Michal Hocko wrote: > On Fri 19-01-18 08:09:08, Petr Tesarik wrote: > [...] > > diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h > > index 67f2e3c38939..7522a6987595 100644 > > --- a/include/linux/mmzone.h > > +++ b/include/linux/mmzone.h > > @@ -1166,8 +1166,16 @@ extern unsigned long usemap_size(void); > > > > /* > > * We use the lower bits of the mem_map pointer to store > > - * a little bit of information. There should be at least > > - * 3 bits here due to 32-bit alignment. > > + * a little bit of information. The pointer is calculated > > + * as mem_map - section_nr_to_pfn(pnum). The result is > > + * aligned to the minimum alignment of the two values: > > + * 1. All mem_map arrays are page-aligned. > > + * 2. section_nr_to_pfn() always clears PFN_SECTION_SHIFT > > + * lowest bits. PFN_SECTION_SHIFT is arch-specific > > + * (equal SECTION_SIZE_BITS - PAGE_SHIFT), and the > > + * worst combination is powerpc with 256k pages, > > + * which results in PFN_SECTION_SHIFT equal 6. > > + * To sum it up, at least 6 bits are available. > > */ > > This is _much_ better indeed. Do you think we can go one step further > and add BUG_ON into the sparse code to guarantee that every mmemap > is indeed aligned properly so that SECTION_MAP_LAST_BIT-1 bits are never > used? This is easy for the section_nr_to_pfn() part. I'd just add: BUILD_BUG_ON(PFN_SECTION_SHIFT < SECTION_MAP_LAST_BIT); But for the mem_map arrays... Do you mean adding a run-time BUG_ON into all allocation paths? Note that mem_map arrays can be allocated by: a) __earlyonly_bootmem_alloc b) memblock_virt_alloc_try_nid c) memblock_virt_alloc_try_nid_raw d) alloc_remap (only arch/tile still has it) Some allocation paths are in mm/sparse.c, others are mm/sparse-vmemmap.c, so it becomes a bit messy, but since it's a single line in each, it may work. Petr T