From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224RTeJrLL7PkzW/RLcy6Fxbd12+a8w37BprHjvSgrM6+aNdGPYJ58vilNlkvTAO7Hano1Z3 ARC-Seal: i=1; a=rsa-sha256; t=1516480165; cv=none; d=google.com; s=arc-20160816; b=Znw3D0Aedz5ylLyjCkYbcSIzD5w8aoFF3XK4uaP7rruW/kAIG++5zcP9FwwDsoBzZc AiDVBpoJO4XHjmLTaMPpDm6TsLisAK4vy86d6QCqacRK9QdQnvqHNoq2dZmyW518MRh1 MtAIbZGs4ty0MpgFSg3IJ6gX+CfZKUNndpz32Jd1feafOH7GRTOzjo6+crglkNKy9zXh rdj6PjFsJuI7AQXyNWo9wE9MBsj5c24mUz7Wj8WIO0U3B196P6vbmw23whNAaZC7bamA kRA0OiWak38YI1RhBPdSHL4LqfsVnYQsaYTGsF7vNs8pBq1FCXnaj2SuwozCu4a/iLrY OgQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:arc-authentication-results; bh=1b/7qYNFQg5cG0jRCAzgw1X5T7W6XfFunRYUaD9NXOk=; b=VclX8YU0gTyl6TEcbYjZehxpcLGC/HYP93S4UlEuCvHudKFkLT6MZ7/dTbBd0vfggx eXoKGec3PX4eCDVsc2PCLqyH8FCqHkNhxrXL9830SfNesljuyzQnhatLOuuxcdBLTDPB 4fvDIgSPB/o1Yz7azpUcOfWfFQ4nKeYHhX53xYhigOQxHODnqbZ1GR2+ySu2kLxa3GAc 3v6hIMb378x5uy63loVdFlFVGVUgxFrHacaLkvfGfAwrbyRDsn59Haj2Yd8eAdQVUehr a1WGCa4Eem5pdVhKlNscOOxS/xX7vruiK1D3r3qBtdTWG6awjkwntN1Kr0FcvzGKlK5Q Esew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 5.9.137.197 as permitted sender) smtp.mailfrom=bp@alien8.de Authentication-Results: mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 5.9.137.197 as permitted sender) smtp.mailfrom=bp@alien8.de Date: Sat, 20 Jan 2018 21:29:17 +0100 From: Borislav Petkov To: David Woodhouse Cc: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: Re: [PATCH 1/4] x86/cpufeatures: Add Intel feature bits for Speculation Control Message-ID: <20180120202917.wl3ifriy2iyfti4u@pd.tnic> References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> <1516449813-7654-2-git-send-email-dwmw@amazon.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1516449813-7654-2-git-send-email-dwmw@amazon.co.uk> User-Agent: NeoMutt/20170609 (1.8.3) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590114213169258479?= X-GMAIL-MSGID: =?utf-8?q?1590144706033558528?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Sat, Jan 20, 2018 at 12:03:30PM +0000, David Woodhouse wrote: > Add three feature bits exposed by new microcode on Intel CPUs for > speculation control. We would now be up to five bits in CPUID(7).RDX > so take them out of the 'scattered' features and make a proper word > for them instead. ... as that leaf is a pure feature bits leaf. > > Signed-off-by: David Woodhouse > --- > arch/x86/include/asm/cpufeature.h | 7 +++++-- > arch/x86/include/asm/cpufeatures.h | 12 +++++++++--- > arch/x86/include/asm/disabled-features.h | 3 ++- > arch/x86/include/asm/required-features.h | 3 ++- > arch/x86/kernel/cpu/common.c | 1 + > arch/x86/kernel/cpu/scattered.c | 2 -- > 6 files changed, 19 insertions(+), 9 deletions(-) Reviewed-by: Borislav Petkov -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.