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mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=UC897lGy; spf=pass (google.com: domain of mingo.kernel.org@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=mingo.kernel.org@gmail.com Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=UC897lGy; spf=pass (google.com: domain of mingo.kernel.org@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=mingo.kernel.org@gmail.com X-Google-Smtp-Source: AH8x224iU8A19J89lJAd5ZiDM8sPLdN8AW+aaQj8pvCUx8RHdJ+oJ6s88Fc09mEzrPlNLaCTmZ09Lw== Sender: Ingo Molnar Date: Sun, 21 Jan 2018 11:26:22 +0100 From: Ingo Molnar To: David Woodhouse Cc: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: Re: [PATCH v2 5/8] x86/speculation: Add basic support for IBPB Message-ID: <20180121102622.xujqxfliksoe75pm@gmail.com> References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> <1516528149-9370-6-git-send-email-dwmw@amazon.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1516528149-9370-6-git-send-email-dwmw@amazon.co.uk> User-Agent: NeoMutt/20170609 (1.8.3) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195048808685762?= X-GMAIL-MSGID: =?utf-8?q?1590197365529834941?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: * David Woodhouse wrote: > From: Thomas Gleixner > > Expose indirect_branch_prediction_barrier() for use in subsequent patches. > > [karahmed: remove the special-casing of skylake for using IBPB (wtf?), > switch to using ALTERNATIVES instead of static_cpu_has] > [dwmw2: set up ax/cx/dx in the asm too so it gets NOP'd out] > > Signed-off-by: Thomas Gleixner > Signed-off-by: KarimAllah Ahmed > Signed-off-by: David Woodhouse > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/nospec-branch.h | 16 ++++++++++++++++ > arch/x86/kernel/cpu/bugs.c | 7 +++++++ > 3 files changed, 24 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 8c9e5c0..cf28399 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -207,6 +207,7 @@ > #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ > #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ > > +#define X86_FEATURE_IBPB ( 7*32+16) /* Using Indirect Branch Prediction Barrier */ > #define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ > diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h > index 4ad4108..c333c95 100644 > --- a/arch/x86/include/asm/nospec-branch.h > +++ b/arch/x86/include/asm/nospec-branch.h > @@ -218,5 +218,21 @@ static inline void vmexit_fill_RSB(void) > #endif > } > > +static inline void indirect_branch_prediction_barrier(void) > +{ > + unsigned long ax, cx, dx; > + > + asm volatile(ALTERNATIVE("", > + "movl %[msr], %%ecx\n\t" > + "movl %[val], %%eax\n\t" > + "movl $0, %%edx\n\t" > + "wrmsr", > + X86_FEATURE_IBPB) > + : "=a" (ax), "=c" (cx), "=d" (dx) > + : [msr] "i" (MSR_IA32_PRED_CMD), > + [val] "i" (PRED_CMD_IBPB) > + : "memory"); > +} > + > #endif /* __ASSEMBLY__ */ > #endif /* __NOSPEC_BRANCH_H__ */ > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c > index 390b3dc..96548ff 100644 > --- a/arch/x86/kernel/cpu/bugs.c > +++ b/arch/x86/kernel/cpu/bugs.c > @@ -249,6 +249,13 @@ static void __init spectre_v2_select_mitigation(void) > setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); > pr_info("Filling RSB on context switch\n"); > } > + > + /* Initialize Indirect Branch Prediction Barrier if supported */ > + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) || > + boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) { > + setup_force_cpu_cap(X86_FEATURE_IBPB); > + pr_info("Enabling Indirect Branch Prediction Barrier\n"); > + } > } I'd suggest writing out the common 'IBPB' acronym in the messages as well: pr_info("Enabling Indirect Branch Prediction Barrier (IBPB)\n"); Also, the kernel's barrier*() namespace as it exists today is: barrier() barrier_data() I think the better name to introduce would be: barrier_indirect_branch_prediction() to maintain barrier_ as a prefix. Thanks, Ingo