From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933402AbeAYDIh (ORCPT ); Wed, 24 Jan 2018 22:08:37 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:42582 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933331AbeAYDIU (ORCPT ); Wed, 24 Jan 2018 22:08:20 -0500 X-Google-Smtp-Source: AH8x22741rtSwjMNi2fGHQvjyrlflQlgnQ4LmmGIo+zj1ow6O3t5toQ/0J0mH/G5h2i9v2RdOkRuBQ== Subject: [PATCH v2 4/4] RISC-V: Move to the new generic IRQ handler Date: Wed, 24 Jan 2018 19:07:56 -0800 Message-Id: <20180125030756.21787-5-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180125030756.21787-1-palmer@sifive.com> References: <20180125030756.21787-1-palmer@sifive.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, patches@groups.riscv.org, Palmer Dabbelt From: Palmer Dabbelt To: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, tglx@linutronix.de, Christoph Hellwig , Arnd Bergmann Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The old mechanism for handling IRQs on RISC-V was pretty ugly: the arch code looked at the Kconfig entry for our first-level irqchip driver and called into it directly. This patch uses the new 0generic IRQ handling infastructure, which essentially just deletes a bunch of code. This does add an additional load to the interrupt latency, but there's a lot of tuning left to be done there on RISC-V so I think it's OK for now. Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/Kbuild | 1 + arch/riscv/kernel/entry.S | 5 +++-- arch/riscv/kernel/irq.c | 13 ------------- 4 files changed, 5 insertions(+), 15 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2c6adf12713a..e67f42178059 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -35,6 +35,7 @@ config RISCV select THREAD_INFO_IN_TASK select RISCV_IRQ_INTC select RISCV_TIMER + select MULTI_IRQ_HANDLER config MMU def_bool y diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 970460a0b492..e0d0fbe43ca2 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -16,6 +16,7 @@ generic-y += ftrace.h generic-y += futex.h generic-y += hardirq.h generic-y += hash.h +generic-y += handle_irq.h generic-y += hw_irq.h generic-y += ioctl.h generic-y += ioctls.h diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 7404ec222406..a79869151aea 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -166,8 +166,9 @@ ENTRY(handle_exception) /* Handle interrupts */ slli a0, s4, 1 srli a0, a0, 1 - move a1, sp /* pt_regs */ - tail do_IRQ + move a0, sp /* pt_regs */ + REG_L a1, handle_arch_irq + jr a1 1: /* Handle syscalls */ li t0, EXC_SYSCALL diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 328718e8026e..b74cbfbce2d0 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -24,16 +24,3 @@ void __init init_IRQ(void) { irqchip_init(); } - -asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs) -{ -#ifdef CONFIG_RISCV_INTC - /* - * FIXME: We don't want a direct call to riscv_intc_irq here. The plan - * is to put an IRQ domain here and let the interrupt controller - * register with that, but I poked around the arm64 code a bit and - * there might be a better way to do it (ie, something fully generic). - */ - riscv_intc_irq(cause, regs); -#endif -} -- 2.13.6