From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752807AbeBAN3m (ORCPT ); Thu, 1 Feb 2018 08:29:42 -0500 Received: from merlin.infradead.org ([205.233.59.134]:54572 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751467AbeBAN3l (ORCPT ); Thu, 1 Feb 2018 08:29:41 -0500 Date: Thu, 1 Feb 2018 14:29:09 +0100 From: Peter Zijlstra To: Stafford Horne Cc: Will Deacon , Paul McKenney , Jonas Bonn , Stefan Kristiansson , David Howells , Arnd Bergmann , linux-kernel@vger.kernel.org, Thomas Gleixner Subject: Re: asm-generic: Disallow no-op mb() for SMP systems Message-ID: <20180201132909.GW2249@hirez.programming.kicks-ass.net> References: <20180131130034.GR2269@hirez.programming.kicks-ass.net> <20180131131737.GA5097@arm.com> <20180131132610.GT2269@hirez.programming.kicks-ass.net> <20180201122750.GE30895@lianli.shorne-pla.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180201122750.GE30895@lianli.shorne-pla.net> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 01, 2018 at 09:27:50PM +0900, Stafford Horne wrote: > I tried to clarify some of this in the spec v1.2 [0] which help formalize some of > the techniques we used for the SMP implementation. Its probably not perfect, > but I added a section "10. Multicore support" and tried to clarify some things > in section 7 on Atomicity. But it seems I dont cover exactly what are are > mentioning here. In general: > > 1 Secondary cores have memory snooping enabled meaning that any write to a > cached address will cause the cache line to be invalidated. > 2 l.swa (store atomic word) implies a store buffer flush. What about l.lwa? Can that observe 'old' values, or rather, miss values stuck in a remote store buffer? This will then cause the first l.swa to fail, which, per the above, would then sync things up? Which means you get that one extra merry-go-round. > 3 l.msync is used to flush the store buffer > > Also, during the IPI controller review [1] Marc Z asked many similar questions. > I believe he was ok in the end. > > Anyway, > Thanks for thanks for spotting the issue here. For some reason I remember we > did have an l.msync for our mb(). Let me think about and test out this patch > (and the fix to actually define mb) to see if anything comes up. > > Also, I haven't seen any implementations that use WOM. Stefan might know better. So if the strong model has a store buffer, as I think the above says, then it is _NOT_ correct for l.msync to be treated as a NOP, it _must_ flush the store buffer. At which point I think your 'strong' model is basically TSO. So it would be very good to get that spelled out somewhere.