From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Dmitry Osipenko <digetx@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver
Date: Wed, 14 Feb 2018 13:15:46 +0200 [thread overview]
Message-ID: <20180214111546.GR5850@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <20180213103039.GA6764@ulmo>
On Tue, Feb 13, 2018 at 11:30:39AM +0100, Thierry Reding wrote:
> > }
>
> It's odd that we don't have an MC clock on Tegra2. I wonder if perhaps
> we just never implemented one, or it uses one which is always on by
> default. Cc Peter to see if he knows.
We do, it has DT ID TEGRA20_CLK_MC. However, it looks like the modeling is
incorrect for Tegra20. Unlike on Tegra30 where the MC clock can be either
half or the same as the EMC clock, it is always half the EMC clock on
Tegra20. This happens to work because we likely never change the MC clock
and the non-existing bit just reads as 0, which means half the MC clock.
Peter.
next prev parent reply other threads:[~2018-02-14 11:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-12 17:06 [PATCH v2 0/2] Memory controller hot reset Dmitry Osipenko
2018-02-12 17:06 ` [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver Dmitry Osipenko
2018-02-13 10:30 ` Thierry Reding
2018-02-14 11:15 ` Peter De Schrijver [this message]
2018-02-14 15:42 ` Dmitry Osipenko
2018-02-19 2:04 ` Dmitry Osipenko
2018-02-19 2:16 ` Dmitry Osipenko
2018-02-12 17:06 ` [PATCH v2 2/2] memory: tegra: Introduce memory client hot reset API Dmitry Osipenko
2018-02-13 11:24 ` Thierry Reding
2018-02-19 12:35 ` Dmitry Osipenko
2018-02-19 12:44 ` Dmitry Osipenko
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