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x-ptr=pass x-ptr-helo=vger.kernel.org x-ptr-lookup=vger.kernel.org; x-return-mx=pass smtp.domain=vger.kernel.org smtp.result=pass smtp_org.domain=kernel.org smtp_org.result=pass smtp_is_org_domain=no header.domain=microsoft.com header.result=pass header_is_org_domain=yes Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964859AbeCSP7O (ORCPT ); Mon, 19 Mar 2018 11:59:14 -0400 Received: from mail-by2nam01on0118.outbound.protection.outlook.com ([104.47.34.118]:14025 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965047AbeCSP7J (ORCPT ); Mon, 19 Mar 2018 11:59:09 -0400 From: Sasha Levin To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" CC: MaJun , Hanjun Guo , Kefeng Wang , "linuxarm@huawei.com" , Wei Yongjun , Thomas Gleixner , Sasha Levin Subject: [PATCH AUTOSEL for 4.9 037/281] irqchip/mbigen: Fix the clear register offset calculation Thread-Topic: [PATCH AUTOSEL for 4.9 037/281] irqchip/mbigen: Fix the clear register offset calculation Thread-Index: AQHTv5siAnk9DXECuUyaVkFohBHn/g== Date: Mon, 19 Mar 2018 15:58:34 +0000 Message-ID: <20180319155742.13731-37-alexander.levin@microsoft.com> References: <20180319155742.13731-1-alexander.levin@microsoft.com> In-Reply-To: <20180319155742.13731-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0726;7:ze2hcy6hw77Fk0zWtoXe1uIBFpty72qHdUMSXwBPMrd3WbAuYpvhDeleEZH9HKPJYNJW+MJEK2zlSAUO3z79kiWg+1kJpG1kzzVW1VVX3GzcXWE0BWcUuBdvE5mSchv3fQG1zgPtiQjdq4RfErTcN9p00pnFlDnm2joPK7r46R9FBi8OfbdgY4pJZEkXw95HL4gFfRz5gNMGKX764SEA2oPE4iqXN4CmsshvDFe/sZ95PtJOO0DZC/yjeNZZu2b5;20:kODt1CZJGsxiuadSjvUaQKzXZwmoxtHWvd2jsagUQxEmRmIvPkyLGtejFpzF5usx8xtWyst5NmbRev6bhCs1iGttGUrG539wgTSNPdmsrEuCnrZJwkpP1ZUY5Xtnt7yueQsUn7ci8/FFAoL3pTgTxQbXY2gMMh+B2NpuZltRBWA= x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 910deda1-1311-4314-4ed7-08d58db254f3 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7193020);SRVR:DM5PR2101MB0726; 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x-microsoft-antispam-message-info: yUgtH64TPBPXW59vf3WSJbM4w5BCyXFuBl4/L76Vvr3rFtkScIojzHLD+Qbrfcj7wguUGF1cYE+pQg3Fc8M7UdqJRuxSENk/ro+XnNnviFqbj/TKx8AImD3Hn9rV+MG50Irwq/UJPI8wTkugqhY3OnwHucoOJmt22w9FtOIYUBN3h6VGW0C2a6aAYCEM2lnITPROwXuwKIP19eIotR7pTndEfPDU/72yAeBOsxpe8hzVBo+c0Cibflm/+bALNAvnHnQ/aeTX/E8vNryCQHtrYTbVKEA1QAfWYcGS5Xc5W0MSVBOv+GiqpFr5cUnZH2hPxEj4chcg1xisFJfxy/TfZA== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 910deda1-1311-4314-4ed7-08d58db254f3 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Mar 2018 15:58:34.0883 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0726 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: MaJun [ Upstream commit 9459a04b6a5a09967eec94a1b66f0a74312819d9 ] The register array offset for clearing an interrupt is calculated by: offset =3D (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / 32; This is wrong because the clear register array includes the reserved interrupts. So the clear operation ends up in the wrong register. This went unnoticed so far, because the hardware clears the real bit through a timeout mechanism when the hardware is configured in debug mode. That debug mode was enabled on early generations of the hardware, so the problem was papered over. On newer hardware with updated firmware the debug mode was disabled, so the bits did not get cleared which causes the system to malfunction. Remove the subtraction of RESERVED_IRQ_PER_MBIGEN_CHIP, so the correct register is accessed. [ tglx: Rewrote changelog ] Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operati= on functions") Signed-off-by: MaJun Signed-off-by: Hanjun Guo Acked-by: Marc Zyngier Cc: Kefeng Wang Cc: linuxarm@huawei.com Cc: Wei Yongjun Link: http://lkml.kernel.org/r/1494561328-39514-4-git-send-email-guohanjun@= huawei.com Signed-off-by: Thomas Gleixner Signed-off-by: Sasha Levin --- drivers/irqchip/irq-mbigen.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 03b79b061d24..05d87f60d929 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -105,10 +105,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t= hwirq, static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, u32 *mask, u32 *addr) { - unsigned int ofst; - - hwirq -=3D RESERVED_IRQ_PER_MBIGEN_CHIP; - ofst =3D hwirq / 32 * 4; + unsigned int ofst =3D (hwirq / 32) * 4; =20 *mask =3D 1 << (hwirq % 32); *addr =3D ofst + REG_MBIGEN_CLEAR_OFFSET; --=20 2.14.1