From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752935AbeC1DCZ (ORCPT ); Tue, 27 Mar 2018 23:02:25 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:62686 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752715AbeC1DB6 (ORCPT ); Tue, 27 Mar 2018 23:01:58 -0400 From: Yixun Lan To: Kevin Hilman CC: Yixun Lan , Carlo Caione , Rob Herring , Qiufang Dai , , , , Subject: [PATCH v3 2/3] ARM64: dts: meson-axg: add an 32K alt aoclk Date: Wed, 28 Mar 2018 11:01:29 +0800 Message-ID: <20180328030130.240336-3-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180328030130.240336-1-yixun.lan@amlogic.com> References: <20180328030130.240336-1-yixun.lan@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.20.235] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Acked-by: Jerome Brunet Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b0eff7d7f771..40ca49fb94a6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -108,6 +108,13 @@ #clock-cells = <0>; }; + ao_alt_xtal: ao_alt_xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <32000000>; + clock-output-names = "ao_alt_xtal"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; -- 2.15.1