From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753050AbeC1ThV (ORCPT ); Wed, 28 Mar 2018 15:37:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:60120 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752416AbeC1ThT (ORCPT ); Wed, 28 Mar 2018 15:37:19 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4034F21773 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=helgaas@kernel.org Date: Wed, 28 Mar 2018 14:37:17 -0500 From: Bjorn Helgaas To: Alan Douglas Cc: Niklas Cassel , "kishon@ti.com" , "cyrille.pitchen@free-electrons.com" , Bjorn Helgaas , Niklas Cassel , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Lorenzo Pieralisi Subject: Re: [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up Message-ID: <20180328193717.GA97213@bhelgaas-glaptop.roam.corp.google.com> References: <20180328115018.31921-1-niklas.cassel@axis.com> <20180328115018.31921-8-niklas.cassel@axis.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [+cc Lorenzo] On Wed, Mar 28, 2018 at 01:24:10PM +0000, Alan Douglas wrote: > > On 28/03/2018 12:51, Niklas Cassel wrote: > > cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means that a 64-bit BAR can be set-up, even when the flag > > PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set. > > > If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64, so that the calling function can know what BAR width that was actually set-up. > > > I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to fix, since there might be a reason why > this flag is ignored. > Will investigate and fix this in future patch > > > Signed-off-by: Niklas Cassel > > --- > > drivers/pci/cadence/pcie-cadence-ep.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c > > index cef36cd6b710..2905e098678c 100644 > > --- a/drivers/pci/cadence/pcie-cadence-ep.c > > +++ b/drivers/pci/cadence/pcie-cadence-ep.c > > @@ -106,6 +106,9 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, > > if (is_64bits && (bar & 1)) > > return -EINVAL; > > > > + if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) > > + epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; > > + > > if (is_64bits && is_prefetch) > > ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; > > else if (is_prefetch) > > -- > > 2.14.2 > Change looks good to me. It will be helpful to Lorenzo if you spell this out, e.g., Acked-by: Alan Douglas Also, it looks like we need a MAINTAINERS update to add drivers/pci/cadence/ to the "PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" filename patterns.