From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751538AbeDERSq (ORCPT ); Thu, 5 Apr 2018 13:18:46 -0400 Received: from mail-by2nam03on0060.outbound.protection.outlook.com ([104.47.42.60]:24093 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751255AbeDERSn (ORCPT ); Thu, 5 Apr 2018 13:18:43 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Yuri.Norov@cavium.com; From: Yury Norov To: "Paul E. McKenney" , Mark Rutland , Will Deacon , Chris Metcalf , Christopher Lameter , Russell King - ARM Linux , Steven Rostedt , Mathieu Desnoyers , Catalin Marinas , Pekka Enberg , David Rientjes , Joonsoo Kim , Andrew Morton , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Alexey Klimov Cc: Yury Norov , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] arm64: entry: isb in el1_irq Date: Thu, 5 Apr 2018 20:17:56 +0300 Message-Id: <20180405171800.5648-2-ynorov@caviumnetworks.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180405171800.5648-1-ynorov@caviumnetworks.com> References: <20180405171800.5648-1-ynorov@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [50.233.148.156] X-ClientProxiedBy: DB6P190CA0021.EURP190.PROD.OUTLOOK.COM (2603:10a6:6:2f::34) To BN6PR07MB2897.namprd07.prod.outlook.com (2603:10b6:404:41::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fa5028c9-c1b6-4cd2-282a-08d59b1945d9 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(5600026)(4604075)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);SRVR:BN6PR07MB2897; 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Target core calls isb() in IPI handler path, but not at the beginning of el1_irq entry. There's a chance that modified instruction will appear prior isb(), and so will not be observed. This patch inserts isb early at el1_irq entry to avoid that chance. Signed-off-by: Yury Norov --- arch/arm64/kernel/entry.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index ec2ee720e33e..9c06b4b80060 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -593,6 +593,7 @@ ENDPROC(el1_sync) .align 6 el1_irq: + isb // pairs with aarch64_insn_patch_text kernel_entry 1 enable_da_f #ifdef CONFIG_TRACE_IRQFLAGS -- 2.14.1