From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752202AbeDHHA0 (ORCPT ); Sun, 8 Apr 2018 03:00:26 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:44175 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751040AbeDHG76 (ORCPT ); Sun, 8 Apr 2018 02:59:58 -0400 From: Yixun Lan To: Marc Zyngier , Jason Cooper , Thomas Gleixner , Kevin Hilman CC: Yixun Lan , Carlo Caione , Jerome Brunet , Heiner Kallweit , Rob Herring , Xingyu Chen , , , , Subject: [PATCH 2/3] dt-bindings: interrupt-controller: New binding for Meson-AXG SoC Date: Sun, 8 Apr 2018 14:56:59 +0000 Message-ID: <20180408145700.23520-3-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180408145700.23520-1-yixun.lan@amlogic.com> References: <20180408145700.23520-1-yixun.lan@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.20.250] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the dt-binding documentation to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-AXG SoC. Signed-off-by: Yixun Lan --- .../devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index c753d99d43db..89674ad8a097 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -14,6 +14,7 @@ Required properties: "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) + "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) - interrupt-parent : a phandle to the GIC the interrupts are routed to. Usually this is provided at the root level of the device tree as it is common to most of the SoC. -- 2.16.2