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Sun, 8 Apr 2018 20:29:47 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Thomas Petazzoni , Marc Zyngier , Sasha Levin Subject: [PATCH AUTOSEL for 4.9 119/293] irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time Thread-Topic: [PATCH AUTOSEL for 4.9 119/293] irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time Thread-Index: AQHTz5kdHxUuK3qSjEiaeMsWS7vg5w== Date: Mon, 9 Apr 2018 00:24:25 +0000 Message-ID: <20180409002239.163177-119-alexander.levin@microsoft.com> References: <20180409002239.163177-1-alexander.levin@microsoft.com> In-Reply-To: <20180409002239.163177-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB1032;7:v07iyxXGk1kdQ3z0I2ULRQ36bBGnWDd5EDv/0GYTdZuesNjh6+jAwLUGcI8rpO5ehwC3q1/MbDxFtMryz+LBrNZgIg88JEBxdSAZ7v2PnpVGKGJzWEw54mtam3r4g/a5Yr0xf9qIn+h4K7GtpFWz8tXLEMQjaK11gFUqjUT8c64RURQymKZusVVf56zI02CLGTfjKdk/YYW+EsOCF/U+iD/gbXfyoPDn0tS8HsavpPt0xzLVw2gG1nU1pU9LCkIV;20:XxKqwfqOCNGGTXU+CBYAgeHAHJlJtn+w23/NLZ9Gco+qQUs+DNe3amTQ6YIPx4ndK9HM2xAmykKAcyMhCtpAnWfL7GxNx7/ECUWAuGx9B5k6kvSS75cP7cEn89octCNLPY5PBPpaQMwyuXsDXMJB0hSag42hxb1PkYatYpxFIDg= x-ms-office365-filtering-ht: Tenant X-MS-Office365-Filtering-Correlation-Id: b9e03f67-0ea4-4628-cbf3-08d59db0fcfd x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7193020);SRVR:DM5PR2101MB1032; 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x-microsoft-antispam-message-info: eV7sbAH9awN70QHjab58iKQ3Gk6QmES9rIQ8CulfNVyjZr76JXHZfJy9aD1NWTxqfaa4TCmAaFbD+pV9DfmDnYrKSN3edGJZY5uN+Tb/Di1hmBXJVY5sG/lyykPjP/kW8t57T0khOJExFqvxvIESoH/W5eAX/4Clwh8jeGkp7+D9h619BxU2xZAciRx8SBkBxzBSW99khpBokrI/tveNAeACJAB7Z967+XPLLJTTLWMygKRZsMfSmiumRcFwKt0MYaKatT4+HdEV6l74w5cYr38pnD50DHpNWrb6imRZbXhjCdLPoBD1DDj7HfX6cQ5n49MQ3gp24zsVBBXQWEC6vFoJAXOTpB29XcJc5KG8IahID9imBa7l3zlTAxemtx1OULAfTrAJmpj5ch8ihdK42iq5vNDJnA2JXuzmbUT6aUI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: b9e03f67-0ea4-4628-cbf3-08d59db0fcfd X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:24:25.9094 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB1032 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Thomas Petazzoni [ Upstream commit 0fa4ce746d1d8c8aa3d09fbc675497fa4c4a5475 ] Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to irq_set_probe(). While the commit log seems to imply that there are no functional changes, there are indeed functional changes introduced by this commit: the IRQ_NOAUTOEN flag is no longer cleared. This functional change caused a regression on Armada XP, which no longer works properly after suspend/resume because per-CPU interrupts remain disabled. This regression was temporarly worked around in commit 353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit implements the solution that was initially discussed with Thomas Gleixner. Due to how the hardware registers work, the irq-armada-370-xp cannot simply save/restore a bunch of registers at suspend/resume to make sure that the interrupts remain in the same state after resuming. Therefore, it relies on the kernel to say whether the interrupt is disabled or not, using the irqd_irq_disabled() function. This was all working fine while the IRQ_NOAUTOEN flag was cleared. With the change introduced by Rob Herring in d17cab4451df1, the IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled() returns false for per-CPU interrupts, and therefore our per-CPU interrupts are no longer re-enabled after resume. This commit fixes that by using irqd_irq_disabled() only for global interrupts, and using the newly introduced irq_percpu_is_enabled() for per-CPU interrupts. Also, it fixes a related problems that per-CPU interrupts were only re-enabled on the boot CPU and not other CPUs. Until now this wasn't a problem since on this platform, only the local timers are using per-CPU interrupts and the local timers of secondary CPUs are turned off/on during CPU hotplug before suspend, after after resume. However, since Linux 4.4, we are also be using per-CPU interrupts for the network controller, so we need to properly restore the per-CPU interrupts on secondary CPUs as well. Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier Signed-off-by: Sasha Levin --- drivers/irqchip/irq-armada-370-xp.c | 46 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-arma= da-370-xp.c index 8bcee65a0b8c..08cd669dc1e2 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -281,7 +281,6 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain= *h, irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_percpu_devid_irq); - } else { irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_level_irq); @@ -345,16 +344,40 @@ static void armada_mpic_send_doorbell(const struct cp= umask *mask, ARMADA_370_XP_SW_TRIG_INT_OFFS); } =20 +static void armada_xp_mpic_reenable_percpu(void) +{ + unsigned int irq; + + /* Re-enable per-CPU interrupts that were enabled before suspend */ + for (irq =3D 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) { + struct irq_data *data; + int virq; + + virq =3D irq_linear_revmap(armada_370_xp_mpic_domain, irq); + if (virq =3D=3D 0) + continue; + + data =3D irq_get_irq_data(virq); + + if (!irq_percpu_is_enabled(virq)) + continue; + + armada_370_xp_irq_unmask(data); + } +} + static int armada_xp_mpic_starting_cpu(unsigned int cpu) { armada_xp_mpic_perf_init(); armada_xp_mpic_smp_cpu_init(); + armada_xp_mpic_reenable_percpu(); return 0; } =20 static int mpic_cascaded_starting_cpu(unsigned int cpu) { armada_xp_mpic_perf_init(); + armada_xp_mpic_reenable_percpu(); enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); return 0; } @@ -502,16 +525,27 @@ static void armada_370_xp_mpic_resume(void) if (virq =3D=3D 0) continue; =20 - if (!is_percpu_irq(irq)) + data =3D irq_get_irq_data(virq); + + if (!is_percpu_irq(irq)) { + /* Non per-CPU interrupts */ writel(irq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - else + if (!irqd_irq_disabled(data)) + armada_370_xp_irq_unmask(data); + } else { + /* Per-CPU interrupts */ writel(irq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); =20 - data =3D irq_get_irq_data(virq); - if (!irqd_irq_disabled(data)) - armada_370_xp_irq_unmask(data); + /* + * Re-enable on the current CPU, + * armada_xp_mpic_reenable_percpu() will take + * care of secondary CPUs when they come up. + */ + if (irq_percpu_is_enabled(virq)) + armada_370_xp_irq_unmask(data); + } } =20 /* Reconfigure doorbells for IPIs and MSIs */ --=20 2.15.1