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Sun, 8 Apr 2018 20:30:32 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Matt Weber , John Linn , Paresh Chaudhary , Wolfram Sang , Sasha Levin Subject: [PATCH AUTOSEL for 4.9 136/293] i2c: cadance: fix ctrl/addr reg write order Thread-Topic: [PATCH AUTOSEL for 4.9 136/293] i2c: cadance: fix ctrl/addr reg write order Thread-Index: AQHTz5kllWHp2SzIXEyjOB7OaBSJQQ== Date: Mon, 9 Apr 2018 00:24:39 +0000 Message-ID: <20180409002239.163177-136-alexander.levin@microsoft.com> References: <20180409002239.163177-1-alexander.levin@microsoft.com> In-Reply-To: <20180409002239.163177-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0807;7:g1hwOE51cao5XadG7cTJ54Q/kTvcQQ5IxSPJvhrMdjDcgdfVqwVUzRhM8zm1bIW02zIcN13sd4Xkg1IxO6mwD6tOCUzM+/qf+sz4S8wmqx887sHZ363hl7erHKTy9AXRU35ctWiSW61ADdRa6xnlF4uq7A6v+RXTBLDtW9iYtjtYDJn1OtXTDkh1nhRAsfz7ZHMBxBhuCLF7uBlx623g4T27ScV/0RwN1oPT0H2f6HGXN781RW9tFwSU3V7DVHzk;20:mtnfkd4N+0kc8wzUFHIfXqvbRhS9K69raygQ9aNQi9zUfim7qfHZOfntIt6P6Vwf0RPIZDwFnimrSQTbCn5xnGfQCAV2ZWsdfRZzAcubtkqOGjmH/7ACcf3Jr7RW/GxesECiJKFjjogeGwLHt7Uh/pcRDlVj8z4wn0TUt7cgMU8= x-ms-office365-filtering-ht: Tenant X-MS-Office365-Filtering-Correlation-Id: 84adb3b2-21e3-4ad5-6db9-08d59db1170a x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7193020);SRVR:DM5PR2101MB0807; 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x-microsoft-antispam-message-info: dcYPSKmPgXwkbeFk7YCf7b50SW1vaRflYalOq7UYVf+arEzqbMg3qcr6S2OaYIf/ctCu+YMr4MZOepMqbOti96+AfCjRfjIPEXde0mZJtwNyXCj6Rz9ixrFabB5aoaVZ69oTwMRpkRZaiqysSHYnXJi66VYBu4fyRzcmyUJbt56rMCcbryKdFm4sLMFp3bIy+kGGgjNMzZ9Eq184RLsgvfT49o10EviDc8p8czPFCbHBeNuENYjgQ4oW4gfsJ+SgLdNCWSjXAW4CjoRZkEtiy32f27zGjAVmEx6N9zLY/6uhumvHzGvU8RTMhHNJQTSFSZqO1zgLQ8aOGQlUgdnOX0KKkvc+IY8OgbqwLXAoseAeZWP7df1sp2evqa2KGvUAxRTr+mPnBisrGcpKTy/ereN5pjIDsbweiKfWAe06T7k= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 84adb3b2-21e3-4ad5-6db9-08d59db1170a X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:24:39.0500 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0807 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Matt Weber [ Upstream commit 8064c616984eaa015f018dba595d78cd24a0cc8c ] The driver was clearing the hold bit in the control register before writing to the address register which resulted in a stop condition being generated rather than a repeated start. This issue was only observed when a system was running much slower than a normal processor would execute. The IP data sheet mentions a ordering of writing to the address register before clearing the hold. Fixes: df8eb5691c4 ("i2c: Add driver for Cadence I2C controller") Signed-off-by: John Linn Signed-off-by: Paresh Chaudhary Signed-off-by: Matthew Weber Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-cadence.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cade= nce.c index 45d6771fac8c..75d80161931f 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -405,14 +405,14 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); } =20 + /* Set the slave address in address register - triggers operation */ + cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, + CDNS_I2C_ADDR_OFFSET); /* Clear the bus hold flag if bytes to receive is less than FIFO size */ if (!id->bus_hold_flag && ((id->p_msg->flags & I2C_M_RECV_LEN) !=3D I2C_M_RECV_LEN) && (id->recv_count <=3D CDNS_I2C_FIFO_DEPTH)) cdns_i2c_clear_bus_hold(id); - /* Set the slave address in address register - triggers operation */ - cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, - CDNS_I2C_ADDR_OFFSET); cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); } =20 --=20 2.15.1