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Sun, 8 Apr 2018 20:31:23 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Paul Burton , "linux-mips@linux-mips.org" , Ralf Baechle , Sasha Levin Subject: [PATCH AUTOSEL for 4.9 169/293] MIPS: CPS: Prevent multi-core with dcache aliasing Thread-Topic: [PATCH AUTOSEL for 4.9 169/293] MIPS: CPS: Prevent multi-core with dcache aliasing Thread-Index: AQHTz5k1mYnjTrjHV0+WKCUT8mJD5Q== Date: Mon, 9 Apr 2018 00:25:06 +0000 Message-ID: <20180409002239.163177-169-alexander.levin@microsoft.com> References: <20180409002239.163177-1-alexander.levin@microsoft.com> In-Reply-To: <20180409002239.163177-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0917;7:MJfDGnMaU83ry/RdR4+x6PtdyWTS6lEaqvhUJatGOPPvPP6hgAYtJSBozOHyQX2wLWX1aE3WPIIU7E0V8u5PgTYaGFLmSiTqtUW830k4B5bfs3sD9NYm9ZegjBibdv5woOlIBYjqnUW4rvGUwaXp5eLCcLrZ/F78xvq1mOGyCYQpXy2W99cObODQGo+qJVNwJRSqpoLLVxTF+RrFPuzFrZKPLzAJByBnxAVq3u8+uE+DJK4FpjcBripe+b4xX5oB;20:d3+hnvvJgZnBtocJhz5thprxXB3xA2DNYINTIkdeeB34LTaHFfLxgg9i2yIB8sjtGWbIoNTol5Z4TeVkbb7RHDWGrbqvMucGCuE7uI4OqA4qgm+J7g7wJjIeG8Tm3ZsTnIekGRoEve9+ZP6+IrmqdttVXTUZVSWuLhyoJivAg64= X-MS-Office365-Filtering-Correlation-Id: b3714986-f084-4211-6962-08d59db1355d x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(4534165)(4627221)(201703031133081)(201702281549075)(5600026)(4604075)(3008032)(48565401081)(2017052603328)(7193020);SRVR:DM5PR2101MB0917; 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x-microsoft-antispam-message-info: A8UIymRzetnnlo3c/mf1FeMJKShBikiqSKi3ry51xARKk+A1cYwANRBh7JO9KszqhYG6/Rhp02dXIlGE9028I1/RdLu6m0THxoN+/obn3EEVItFzN4l5kiZ0PrnbWg4pJcCLS6tHh+yHFSLBV1bVdBwKf6FhJIti40xJ9qxVim6TySZIYJuCFSwjmg8K1XZ/AfNCQIpJr1tjFXJMzETSbbOqG0iHAxNCEj5hrG3ggaF8xM5g0tqZVDBi0OI5QdTyDRIF/bm/Iz1PL8VrCiYvSw7Ip1Jq8UZ1CgbmDrvJYhMC8Zbi6HU2z4r9HaMeg1x44xrrQ8cAVYTh/fP6A9DsVxmcj+33QnuhCrzav0+u9FMJI6hbMLPH2AR8djbhgOTjHOa7xPbP+3WYNrwS3o1VUzCtejdGVLc8MG5AlAGbMAI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: b3714986-f084-4211-6962-08d59db1355d X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:25:06.5657 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0917 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Paul Burton [ Upstream commit 5570ba2ee920de4e7760a2802b842771845b2c32 ] Systems using the MIPS Coherence Manager (CM) cannot support multi-core SMP with dcache aliasing. This is because CPU caches are VIPT, but interventions in CM-based systems provide only the physical address to remote caches. This means that interventions may behave incorrectly in the presence of an aliasing dcache, since the physical address used when handling an intervention may lead to operation on an aliased cache line rather than the correct line. Prevent us from running into this issue by refusing to boot secondary cores in systems where dcache aliasing may occur. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16196/ Signed-off-by: Ralf Baechle Signed-off-by: Sasha Levin --- arch/mips/kernel/smp-cps.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 6183ad84cc73..63c8136d5132 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -140,9 +140,11 @@ static void __init cps_prepare_cpus(unsigned int max_c= pus) =20 /* Warn the user if the CCA prevents multi-core */ ncores =3D mips_cm_numcores(); - if (cca_unsuitable && ncores > 1) { - pr_warn("Using only one core due to unsuitable CCA 0x%x\n", - cca); + if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) { + pr_warn("Using only one core due to %s%s%s\n", + cca_unsuitable ? "unsuitable CCA" : "", + (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", + cpu_has_dc_aliases ? "dcache aliasing" : ""); =20 for_each_present_cpu(c) { if (cpu_data[c].core) --=20 2.15.1