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Miller" , Sasha Levin Subject: [PATCH AUTOSEL for 4.9 227/293] net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b Thread-Topic: [PATCH AUTOSEL for 4.9 227/293] net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b Thread-Index: AQHTz5lQDh0SZu+owEuTmwD9TPCIDg== Date: Mon, 9 Apr 2018 00:25:51 +0000 Message-ID: <20180409002239.163177-227-alexander.levin@microsoft.com> References: <20180409002239.163177-1-alexander.levin@microsoft.com> In-Reply-To: <20180409002239.163177-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0902;7:ruFthmnkOiqBVIxOVNRQII6h5pN9bNoXEOHegw8S5DHkTIAqHrpqV2MD85gtWqCqxMY8HRmipR9gyHKPNS9VkqLORSE4eXKr6uPMn5EXV6R8dNDkIA1j7k20BdrNnVsZH35o2cu01WqcfwNYG46r6FfC25+JMg25Bp3hVMKNSWyfv8WUw0xxCfWaQSBHVoxqY4RFpCY3Iwv4GHP76EeCGQYJG0/UdaAxnR1nOB2Ps2FtWq+9KiFZrXGV+xmDM536;20:RFVJDyta7oWTszy+COjzxaUUE9PBy52EAseJAxZXQv9nsPiII7gfrOhrQ21hRbGX/1RM2poZHYtTTEKUZ7j6gMzIvY7MeKvq7h8OWwVn6dAINDlXuzKRf5VMZ7Dut3p4YzGm42KXj9hTxehL3STWDtxu5rps+qDXDU3DV25xFSI= x-ms-office365-filtering-ht: Tenant X-MS-Office365-Filtering-Correlation-Id: 031d1eec-9d4c-4c2c-999d-08d59db17077 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7193020);SRVR:DM5PR2101MB0902; x-ms-traffictypediagnostic: DM5PR2101MB0902: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alexander.Levin@microsoft.com; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(28532068793085)(89211679590171)(8415204561270)(17755550239193); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(61425038)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231221)(944501327)(52105095)(3002001)(10201501046)(6055026)(61426038)(61427038)(6041310)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(6072148)(201708071742011);SRVR:DM5PR2101MB0902;BCL:0;PCL:0;RULEID:;SRVR:DM5PR2101MB0902; x-forefront-prvs: 0637FCE711 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(366004)(376002)(396003)(39860400002)(39380400002)(346002)(199004)(189003)(5660300001)(478600001)(86612001)(3846002)(6116002)(106356001)(25786009)(6486002)(72206003)(10290500003)(8936002)(6436002)(76176011)(2616005)(6506007)(2900100001)(97736004)(26005)(486006)(10090500001)(36756003)(81166006)(8676002)(81156014)(59450400001)(102836004)(2906002)(99286004)(11346002)(476003)(3660700001)(66066001)(6512007)(86362001)(53936002)(105586002)(186003)(5250100002)(14454004)(22452003)(6666003)(2501003)(446003)(7736002)(316002)(1076002)(110136005)(3280700002)(68736007)(54906003)(107886003)(4326008)(305945005)(22906009)(32563001)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:DM5PR2101MB0902;H:DM5PR2101MB1032.namprd21.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; x-microsoft-antispam-message-info: TbWsZONoBz+JcidapraikU2hsXuhyEI5iKoBlNMQW8ERXWcs95Da+2LJ0W/6sixHueD6jCsIYmX2FMzCPACAwymxVDjbIxG++6yYNn8otSrSzvDReYE53eCMujKZzOIekMDO5KhAOUMDXcIHMVXq1oDfIX82Oc/2hqFx0AvXCHSauuWwfvlGeV/KqrkpYRXo9qPepkHp+qOwWEBkj+ftqUWKDgNPgc7w1bHXaPIhwrlP8i+ZIWtHApbk58lWthkAycNqW4t2oyAbMfZqGlUcOS35VXO3up+uckaavy9m1fYGhTrAFRh/1HxM8GuPlx7E1tzFSy7qMRgN4dec4hHNLaDMT59RKTkm0g0vhmDLlbZUeauJd+2O/rk+aGqIm/ZIae56mPm1vIwQlnVbmBR9S1/zuuKMl+DviDnyW5eTY4E= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 031d1eec-9d4c-4c2c-999d-08d59db17077 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:25:51.2067 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0902 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Martin Blumenstingl [ Upstream commit 433c6cab9d298687c097f6ee82e49157044dc7c6 ] Meson8b only supports MPLL2 as clock input. The rate of the MPLL2 clock set by Odroid-C1's u-boot is close to (but not exactly) 500MHz. The exact rate is 500002394Hz, which is calculated in drivers/clk/meson/clk-mpll.c using the following formula: DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, (SDM_DEN * n2) + sdm) Odroid-C1's u-boot configures MPLL2 with the following values: - SDM_DEN =3D 16384 - SDM =3D 1638 - N2 =3D 5 The 250MHz clock (m250_div) inside dwmac-meson8b driver is derived from the MPLL2 clock. Due to MPLL2 running slightly faster than 500MHz the common clock framework chooses a divider which is too big to generate the 250MHz clock (a divider of 2 would be needed, but this is rounded up to a divider of 3). This breaks the RTL8211F RGMII PHY on Odroid-C1 because it requires a (close to) 125MHz RGMII TX clock (on Gbit speeds, the IP block internally divides that down to 25MHz on 100Mbit/s connections and 2.5MHz on 10Mbit/s connections - we don't need any special configuration for that). Round the divider to the closest value to prevent this issue on Meson8b. This means we'll now end up with a clock rate for the RGMII TX clock of 125001197Hz (=3D 125MHz plus 1197Hz), which is close-enough to 125MHz. This has no effect on the Meson GX SoCs since there fclk_div2 is used as input clock, which has a rate of 1000MHz (and thus is divisible cleanly to 250MHz and 125MHz). Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meso= n 8b / GXBB DWMAC") Reported-by: Emiliano Ingrassia Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-meson8b.c index ffaed1f35efe..923033867a4d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -146,7 +146,9 @@ static int meson8b_init_clk(struct meson8b_dwmac *dwmac= ) dwmac->m250_div.shift =3D PRG_ETH0_CLK_M250_DIV_SHIFT; dwmac->m250_div.width =3D PRG_ETH0_CLK_M250_DIV_WIDTH; dwmac->m250_div.hw.init =3D &init; - dwmac->m250_div.flags =3D CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; + dwmac->m250_div.flags =3D CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO | + CLK_DIVIDER_ROUND_CLOSEST; =20 dwmac->m250_div_clk =3D devm_clk_register(dev, &dwmac->m250_div.hw); if (WARN_ON(IS_ERR(dwmac->m250_div_clk))) --=20 2.15.1