From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755932AbeDWPV7 (ORCPT ); Mon, 23 Apr 2018 11:21:59 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:54395 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755568AbeDWPU4 (ORCPT ); Mon, 23 Apr 2018 11:20:56 -0400 From: Lionel Debieve To: Alexandre Torgue , Maxime Coquelin , Rob Herring , Mark Rutland , Russell King CC: , , Subject: [PATCH 4/4] ARM: dts: stm32: Add CRC support on stm32mp157c Date: Mon, 23 Apr 2018 17:19:47 +0200 Message-ID: <20180423151947.2526-5-lionel.debieve@st.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180423151947.2526-1-lionel.debieve@st.com> References: <20180423151947.2526-1-lionel.debieve@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.65] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-23_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add CRC instance of the stm32mp157c SoC Signed-off-by: Lionel Debieve --- arch/arm/boot/dts/stm32mp157c.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 5ce7d28f8a1f..2962decacd87 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -185,6 +185,13 @@ status = "disabled"; }; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- 2.15.1