From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752853AbeERJrx (ORCPT ); Fri, 18 May 2018 05:47:53 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:45749 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752208AbeERJru (ORCPT ); Fri, 18 May 2018 05:47:50 -0400 X-Google-Smtp-Source: AB8JxZrV6NVTnozGLmbo3r78a14EeSR0KteEuunpexOEtKnmmBHUSpMNcepadQf2kOtQFi0/3dU4PA== From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Jagan Teki Subject: [PATCH v2 16/26] dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO[0-1] macros Date: Fri, 18 May 2018 15:15:26 +0530 Message-Id: <20180518094536.17201-17-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com> References: <20180518094536.17201-1-jagan@amarulasolutions.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allwinner A64 has two clock parents PLL_VIDEO0 and PLL_VIDEO1. Include these macros on dt-bindings so-that the same can be used while defining CCU clock phadles. Signed-off-by: Jagan Teki --- Changes for v2: - new patch include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index d66432c6e675..d1d7d5b7d06a 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -43,7 +43,9 @@ #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ #define _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define CLK_PLL_VIDEO0 7 #define CLK_PLL_PERIPH0 11 +#define CLK_PLL_VIDEO1 15 #define CLK_BUS_MIPI_DSI 28 #define CLK_BUS_CE 29 -- 2.14.3