From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96AB1C1B0F2 for ; Wed, 20 Jun 2018 13:53:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C6A620836 for ; Wed, 20 Jun 2018 13:53:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C6A620836 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754444AbeFTNxq (ORCPT ); Wed, 20 Jun 2018 09:53:46 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:37544 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754418AbeFTNxo (ORCPT ); Wed, 20 Jun 2018 09:53:44 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC3DC80D; Wed, 20 Jun 2018 06:53:43 -0700 (PDT) Received: from big-swifty.cambridge.arm.com (big-swifty.cambridge.arm.com [10.1.31.224]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D86D73F578; Wed, 20 Jun 2018 06:53:37 -0700 (PDT) From: Marc Zyngier To: linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ard Biesheuvel , Shanker Donthineni , Shameer Kolothum , MaJun , Laurentiu Tudor , Lei Zhang Subject: [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI range Date: Wed, 20 Jun 2018 14:52:33 +0100 Message-Id: <20180620135234.32101-7-marc.zyngier@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180620135234.32101-1-marc.zyngier@arm.com> References: <20180620135234.32101-1-marc.zyngier@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A recent extension to the GIC architecture allows a hypervisor to arbitrarily reduce the number of LPIs available to a guest, no matter what the GIC says about the valid range of IntIDs. Let's factor in this information when computing the number of available LPIs Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 9 +++++++++ include/linux/irqchip/arm-gic-v3.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 8c7e8c235faf..903ca1c19553 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1525,8 +1525,17 @@ static int free_lpi_range(u32 base, u32 nr_lpis) static int __init its_lpi_init(u32 id_bits) { u32 lpis = (1UL << id_bits) - 8192; + u32 numlpis; int err; + numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); + + if (numlpis > 1 && !WARN_ON(numlpis > lpis)) { + lpis = numlpis; + pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", + lpis); + } + /* * Initializing the allocator is just the same as freeing the * full range of LPIs. diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 396cd99af02f..9d2ea3e907d0 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -73,6 +73,7 @@ #define GICD_TYPER_MBIS (1U << 16) #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) +#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) -- 2.17.1