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[24.223.123.72]) by smtp.gmail.com with ESMTPSA id k9-v6sm3919055pgs.49.2018.06.20.08.43.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Jun 2018 08:43:45 -0700 (PDT) Date: Wed, 20 Jun 2018 09:43:44 -0600 From: Rob Herring To: Michel Pollet Cc: linux-renesas-soc@vger.kernel.org, Simon Horman , phil.edworthy@renesas.com, Michel Pollet , Michael Turquette , Stephen Boyd , Mark Rutland , Geert Uytterhoeven , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v9 2/5] dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation Message-ID: <20180620154344.GA32205@rob-hp-laptop> References: <1528973829-25493-1-git-send-email-michel.pollet@bp.renesas.com> <1528973829-25493-3-git-send-email-michel.pollet@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1528973829-25493-3-git-send-email-michel.pollet@bp.renesas.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 14, 2018 at 11:56:31AM +0100, Michel Pollet wrote: > The Renesas R9A06G032 SYSCTRL node description. > > Signed-off-by: Michel Pollet > --- > .../bindings/clock/renesas,r9a06g032-sysctrl.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt One nit, otherwise: Reviewed-by: Rob Herring > > diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > new file mode 100644 > index 0000000..f6cb5e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > @@ -0,0 +1,44 @@ > +* Renesas R9A06G032 SYSCTRL > + > +Required Properties: > + > + - compatible: Must be: > + - "renesas,r9a06g032-sysctrl" > + - reg: Base address and length of the SYSCTRL IO block. > + - #clock-cells: Must be 1 > + - clocks: References to the parent clocks: > + - external 40mhz crystal. > + - external (optional) 32.768khz > + - external (optional) jtag input > + - external (optional) RGMII_REFCLK > + - clock-names: Must be: > + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; > + > +Examples > +-------- > + > + - SYSCTRL node: > + > + sysctrl: system-controller@4000c000 { > + compatible = "renesas,r9a06g032-sysctrl"; > + reg = <0x4000c000 0x1000>; > + status = "okay"; Don't show status in examples. > + #clock-cells = <1>; > + > + clocks = <&ext_mclk>, <&ext_rtc_clk>, > + <&ext_jtag_clk>, <&ext_rgmii_ref>; > + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; > + }; > + > + - Other nodes can use the clocks provided by SYSCTRL as in: > + > + #include > + uart0: serial@40060000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x40060000 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&sysctrl R9A06G032_CLK_UART0>; > + clock-names = "baudclk"; > + }; > -- > 2.7.4 >