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[24.223.123.72]) by smtp.gmail.com with ESMTPSA id r9-v6sm1015262ywl.59.2018.06.20.11.12.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Jun 2018 11:12:46 -0700 (PDT) Date: Wed, 20 Jun 2018 12:12:45 -0600 From: Rob Herring To: Masahiro Yamada Cc: linux-mtd@lists.infradead.org, Boris Brezillon , linux-kbuild@vger.kernel.org, Richard Weinberger , "linux-stable #4 . 14+" , devicetree@vger.kernel.org, Miquel Raynal , linux-kernel@vger.kernel.org, Marek Vasut , Brian Norris , David Woodhouse , Mark Rutland Subject: Re: [PATCH v3 1/3] mtd: rawnand: denali_dt: add more clocks based on IP datasheet Message-ID: <20180620181245.GA30779@rob-hp-laptop> References: <1529025532-22087-1-git-send-email-yamada.masahiro@socionext.com> <1529025532-22087-2-git-send-email-yamada.masahiro@socionext.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1529025532-22087-2-git-send-email-yamada.masahiro@socionext.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 15, 2018 at 10:18:50AM +0900, Masahiro Yamada wrote: > According to the Denali User's Guide, this IP needs three clocks: > > - clk: controller core clock > > - clk_x: bus interface clock > > - ecc_clk: clock at which ECC circuitry is run > > Currently, denali_dt.c requires a single anonymous clock and its > frequency. However, the driver needs to get the frequency of "clk_x" > not "clk". This is confusing because people tend to assume the > anonymous clock means the core clock. In fact, I got a report of > SOCFPGA breakage because the timing parameters are calculated based > on a wrong frequency. > > Instead of the cheesy implementation, the clocks in the real hardware > should be represented in the driver and the DT-binding. > > However, adding new clocks would break the existing platforms. For the > backward compatibility, the driver still accepts a single clock just as > before. If clk_x is missing, clk_x_rate is set to a hardcoded value. > This is fine for existing DT of Socionext UniPhier, and also fixes the > issue of Altera (Intel) SOCFPGA because both platforms use 200 MHz for > the bus interface clock. > > Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by setup_data_interface()") > Cc: linux-stable #4.14+ > Reported-by: Richard Weinberger > Signed-off-by: Masahiro Yamada > --- > > Changes in v3: > - Change the patch order so that the bug-fix one comes the first > > Changes in v2: > - Split patches into sensible chunks > > .../devicetree/bindings/mtd/denali-nand.txt | 5 +++ > drivers/mtd/nand/raw/denali_dt.c | 49 ++++++++++++++++++++-- > 2 files changed, 50 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt > index 0ee8edb..f33da87 100644 > --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt > +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt > @@ -8,6 +8,9 @@ Required properties: > - reg : should contain registers location and length for data and reg. > - reg-names: Should contain the reg names "nand_data" and "denali_reg" > - interrupts : The interrupt number. > + - clocks: should contain phandle of the controller core clock, the bus > + interface clock, and the ECC circuit clock. > + - clock-names: should contain "nand", "nand_x", "ecc" The subject says "add more clocks", but it doesn't look like any clocks were supported before. Or documentation was missing? Please split bindings to a separate patch. Rob