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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id a81-v6sm6038150pfl.167.2018.06.26.13.26.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 13:26:14 -0700 (PDT) Date: Tue, 26 Jun 2018 13:28:39 -0700 From: Bjorn Andersson To: Stephen Boyd Cc: Marc Zyngier , Srinivas Kandagatla , jason@lakedaemon.net, sudeep.holla@arm.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, nicolas.dechesne@linaro.org Subject: Re: [RFC PATCH] irqchip/gic-v3: Add quirk for msm8996 secured registers Message-ID: <20180626202839.GI1860@tuxbook-pro> References: <20180613114340.32550-1-srinivas.kandagatla@linaro.org> <2d866cd1-59a4-befb-b2de-b91f9e56804a@arm.com> <98209e4e-96b3-3baf-3f21-a57dc8447850@linaro.org> <152900843159.16708.3190914824253841690@swboyd.mtv.corp.google.com> <61229c8f-7de0-a798-5af4-ba5e0ea78001@arm.com> <152908522534.16708.13094007571453293776@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <152908522534.16708.13094007571453293776@swboyd.mtv.corp.google.com> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 15 Jun 10:53 PDT 2018, Stephen Boyd wrote: > Quoting Marc Zyngier (2018-06-15 01:16:02) > > On 14/06/18 21:33, Stephen Boyd wrote: > > > Quoting Srinivas Kandagatla (2018-06-14 10:54:43) > > >>> > > >>>> +{ > > >>>> + struct gic_chip_data *d = data; > > >>>> + > > >>>> + d->flags |= GICV3_FLAGS_WORKAROUND_IW_GICR_WAKER; > > >>>> + > > >>>> + return true; > > >>>> +} > > >>>> + > > >>>> +static const struct gic_quirk gicv3_quirks[] = { > > >>>> + { > > >>>> + .desc = "GICV3: Qualcomm MSM8996 WAKER IW", > > >>> > > >>> Please the erratum number in the message. It should read something like: > > >>> > > >>> "GICv3: Qualcomm erratum BIGNUMBERHERE" > > >>> > > >>>> + .iidr = 0x00001070, /* MSM8996 */ > > >>>> + .mask = 0x0000ffff, > > >>> > > >>> Please match the full GICD_IIDR register, not just the implementer and > > >>> the revision. Unless you expect all the QC systems to have the same > > >>> behaviour? > > >> There seems to be more than one SoC that has this issue, I will dig up > > >> more info before sending next version. > > >> > > > > > > It depends on the firmware and if that firmware decides to block or > > > allow access to this register space. I don't see how it can be quirked > > > based on the IIDR at all because there could be different firmware on > > > the board that doesn't block access to the register. Can a DT property > > > work? > > > > Are you saying that the IIDR doesn't isn't unique per implementation of > > the firmware (which, as far as the kernel is concerned in this case, > > implements the GIC)? That would be another erratum. If we did change the > > behaviour of the vGIC in KVM, we'd certainly change the IIDR value! This > > is the exact same case. > > I don't know for certain. All I know is that we can't assume all QC > systems have a firmware that brings the whole system down when you read > the WAKER register. Hopefully Srini can find out if reads to IIDR are > being trapped by the hypervisor and emulated as something different. > I took another look at the internal documentation related to this change and concluded that it was introduced for the "lead device" on the 8996 platform. As such I expect that all publicly available 8996 devices have this implementation. Looking through some relevant platforms it seems like it's only 8996 that that sports a GICv3 with an IIDR of 0x1070 (e.g. 8994 has a QGICv2 with the same IIDR...), so the quirk seems reasonable in scope. Regards, Bjorn