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[24.223.123.72]) by smtp.gmail.com with ESMTPSA id l133-v6sm6200191oif.48.2018.07.05.16.34.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 05 Jul 2018 16:34:01 -0700 (PDT) Date: Thu, 5 Jul 2018 17:34:01 -0600 From: Rob Herring To: Ray Jui Cc: Kishon Vijay Abraham I , Mark Rutland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com Subject: Re: [PATCH v3 1/2] dt-bindings: phy: Add binding doc for Stingray PCIe PHY Message-ID: <20180705233401.GA26079@rob-hp-laptop> References: <1530728533-28770-1-git-send-email-ray.jui@broadcom.com> <1530728533-28770-2-git-send-email-ray.jui@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1530728533-28770-2-git-send-email-ray.jui@broadcom.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 04, 2018 at 11:22:12AM -0700, Ray Jui wrote: > Add binding document for Stingray PCIe PHYs for both PAXB and PAXC based > root complex > > Signed-off-by: Ray Jui > --- > .../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt > > diff --git a/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt > new file mode 100644 > index 0000000..5a13511 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt > @@ -0,0 +1,41 @@ > +Broadcom Stingray PCIe PHY > + > +Required properties: > +- compatible: must be "brcm,sr-pcie-phy" > +- reg: base address and length of the PCIe SS register space > +- brcm,sr-cdru: phandle to the CDRU syscon node > +- brcm,sr-mhb: phandle to the MHB syscon node > +- #phy-cells: Must be 1, denotes the PHY index > + > +For PAXB based root complex, one can have a configuration of up to 8 PHYs > +PHY index goes from 0 to 7 > + > +For the internal PAXC based root complex, PHY index is always 8 > + > +Example: > + mhb: syscon@60401000 { > + compatible = "brcm,sr-mhb", "syscon"; > + reg = <0 0x60401000 0 0x38c>; > + }; > + > + cdru: syscon@6641d000 { > + compatible = "brcm,sr-cdru", "syscon"; > + reg = <0 0x6641d000 0 0x400>; > + }; > + > + pcie_phy: phy { Needs a unit address. With that, Reviewed-by: Rob Herring > + compatible = "brcm,sr-pcie-phy"; > + reg = <0 0x40000000 0 0x800>; > + brcm,sr-cdru = <&cdru>; > + brcm,sr-mhb = <&mhb>; > + #phy-cells = <1>; > + }; > + > + /* users of the PCIe PHY */ > + > + pcie0: pcie@48000000 { > + ... > + ... > + phys = <&pcie_phy 0>; > + phy-names = "pcie-phy"; > + }; > -- > 2.1.4 >