From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 977FDC5CFE7 for ; Mon, 9 Jul 2018 16:48:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 43DDC20852 for ; Mon, 9 Jul 2018 16:48:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ekxfZVEz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 43DDC20852 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933737AbeGIQr3 (ORCPT ); Mon, 9 Jul 2018 12:47:29 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:32980 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933589AbeGIQr0 (ORCPT ); Mon, 9 Jul 2018 12:47:26 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w69Gl45s080862; Mon, 9 Jul 2018 11:47:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1531154824; bh=W0kRDZkVsv0rkhSf+sUTtICVX5B3BkERYvdGBI2zB3o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ekxfZVEzT8gDbz6FFLU6kFCZZnsPLxDlpgp/Wl72daVefcAy+NLgPQxiUNUQdWjKv PV3OdXH/1NZNmnrRvhdGkwdJenrh08SNUvUX0ue0fRmgs14DqwXf4w1EgJJMsK0BwB AfcwQWtviLsw1N3+kEG16j5wQIp9sp4HVhMUkkbM= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w69Gl4qf017858; Mon, 9 Jul 2018 11:47:04 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 9 Jul 2018 11:47:03 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 9 Jul 2018 11:47:03 -0500 Received: from a0230074-OptiPlex-7010.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w69GkpWC001873; Mon, 9 Jul 2018 11:47:00 -0500 From: Faiz Abbas To: , , , , CC: , , , , , , , Subject: [PATCH v5 2/6] clk: ti: dra7: Add clkctrl clock data for the mcan clocks Date: Mon, 9 Jul 2018 22:18:37 +0530 Message-ID: <20180709164841.14182-3-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180709164841.14182-1-faiz_abbas@ti.com> References: <20180709164841.14182-1-faiz_abbas@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add clkctrl data for the m_can clocks and register it within the clkctrl driver Acked-by: Rob Herring Acked-by: Stephen Boyd CC: Tero Kristo Signed-off-by: Faiz Abbas --- drivers/clk/ti/clk-7xx.c | 1 + include/dt-bindings/clock/dra7.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index fb249a1637a5..71a122b2dc67 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -708,6 +708,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, + { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"}, { 0 }, }; diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 5e1061b15aed..d7549c57cac3 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -168,5 +168,6 @@ #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) #endif -- 2.17.0