From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 637E4C5CFEB for ; Mon, 9 Jul 2018 16:47:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F91F20852 for ; Mon, 9 Jul 2018 16:47:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="muJu4uNe" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F91F20852 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933779AbeGIQrk (ORCPT ); Mon, 9 Jul 2018 12:47:40 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45088 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933433AbeGIQrh (ORCPT ); Mon, 9 Jul 2018 12:47:37 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w69GlGsR092195; Mon, 9 Jul 2018 11:47:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1531154836; bh=tmVgVNsYrnik95T+UDRp7GvOZ8LMOe7Zz9+Ew/gWXvw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=muJu4uNe7yssJGx+d6OI/UeeiStQnsOIsk2VEhOca1ZrmmeaCsBSN+dWSUF4ebP/3 8uRPxWPF4Loa17tyUGX9Kme9XSOq/buQwA/zCxh4Y/2pMtxa4NAx04/RdVIpYgeODS ab18fDXf4Fh3ffBlE1opE5GMu2YO4gtT4verEZek= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w69GlGpO018132; Mon, 9 Jul 2018 11:47:16 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 9 Jul 2018 11:47:15 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 9 Jul 2018 11:47:15 -0500 Received: from a0230074-OptiPlex-7010.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w69GkpWF001873; Mon, 9 Jul 2018 11:47:12 -0500 From: Faiz Abbas To: , , , , CC: , , , , , , , Subject: [PATCH v5 5/6] ARM: dts: Add generic interconnect target module node for MCAN Date: Mon, 9 Jul 2018 22:18:40 +0530 Message-ID: <20180709164841.14182-6-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180709164841.14182-1-faiz_abbas@ti.com> References: <20180709164841.14182-1-faiz_abbas@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ti-sysc driver provides support for manipulating the idle modes and interconnect level resets. Add the generic interconnect target module node for MCAN to support the same. CC: Tony Lindgren Signed-off-by: Faiz Abbas --- arch/arm/boot/dts/dra76x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index bfc82636999c..5157cc431574 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -11,6 +11,24 @@ / { compatible = "ti,dra762", "ti,dra7"; + ocp { + target-module@42c01900 { + compatible = "ti,sysc-dra7-mcan", "ti,sysc"; + ranges = <0x0 0x42c00000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x42c01900 0x4>, + <0x42c01904 0x4>, + <0x42c01908 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | + SYSC_DRA7_MCAN_ENAWAKEUP)>; + ti,syss-mask = <1>; + clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>; + clock-names = "fck"; + }; + }; + }; /* MCAN interrupts are hard-wired to irqs 67, 68 */ -- 2.17.0