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[192.55.54.38]) by smtp.gmail.com with ESMTPSA id v15-v6sm2460555pff.120.2018.07.20.05.31.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jul 2018 05:31:42 -0700 (PDT) Received: by kshutemo-mobl1.localdomain (Postfix, from userid 1000) id 40CBD300254; Fri, 20 Jul 2018 15:31:39 +0300 (+03) Date: Fri, 20 Jul 2018 15:31:39 +0300 From: "Kirill A. Shutemov" To: Dave Hansen Cc: "Kirill A. Shutemov" , Ingo Molnar , x86@kernel.org, Thomas Gleixner , "H. Peter Anvin" , Tom Lendacky , Kai Huang , Jacob Pan , linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCHv5 07/19] x86/mm: Mask out KeyID bits from page table entry pfn Message-ID: <20180720123139.2k3tze6rrfnkhksx@kshutemo-mobl1> References: <20180717112029.42378-1-kirill.shutemov@linux.intel.com> <20180717112029.42378-8-kirill.shutemov@linux.intel.com> <9922042b-f130-a87c-8239-9b852e335f26@intel.com> <20180719095404.pkm72iyhhc6v5tth@kshutemo-mobl1> <0c1bdd80-8e47-e65c-f421-0c5010058025@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0c1bdd80-8e47-e65c-f421-0c5010058025@intel.com> User-Agent: NeoMutt/20180622 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 19, 2018 at 07:19:01AM -0700, Dave Hansen wrote: > On 07/19/2018 02:54 AM, Kirill A. Shutemov wrote: > > On Wed, Jul 18, 2018 at 04:13:20PM -0700, Dave Hansen wrote: > >> On 07/17/2018 04:20 AM, Kirill A. Shutemov wrote: > >>> + } else { > >>> + /* > >>> + * Reset __PHYSICAL_MASK. > >>> + * Maybe needed if there's inconsistent configuation > >>> + * between CPUs. > >>> + */ > >>> + physical_mask = (1ULL << __PHYSICAL_MASK_SHIFT) - 1; > >>> + } > >> This seems like an appropriate place for a WARN_ON(). Either that, or > >> axe this code. > > There's pr_err_once() above in the function. > > Do you mean for the (tme_activate != tme_activate_cpu0) check? > > But that's about double-activating this feature. This check is about an > inconsistent configuration between two CPUs which seems totally different. > > Could you explain? (tme_activate != tme_activate_cpu0) check is about inconsistent configuration. It checks if MSR's content on the given CPU matches MSR on CPU0. -- Kirill A. Shutemov