From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B50CECDFB8 for ; Tue, 24 Jul 2018 17:31:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1067F20880 for ; Tue, 24 Jul 2018 17:31:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="zNYcsLLw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1067F20880 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388524AbeGXSil (ORCPT ); Tue, 24 Jul 2018 14:38:41 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:34506 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388324AbeGXSik (ORCPT ); Tue, 24 Jul 2018 14:38:40 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w6OHV2sN014322; Tue, 24 Jul 2018 12:31:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1532453462; bh=r4QmPBPfwvBfvwSOY7PvLeKWRHtXCotnnhf+u63NpB8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zNYcsLLw1Q5CkxLRTIIrxbPDejaShxuJ9Pxd20L3kHaPzlIZJhCNVBtOWNCmQzHC8 aopfD6X5Rom6MNG19PlAvtL7H6gPuVTIfB3QsengIN6rjsH31dUEtNybFPcgguz+CF iqqKBP1DtwT1ejx3L/RAgi2j3jolRklddaaDnDm0= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w6OHV2Kq010821; Tue, 24 Jul 2018 12:31:02 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 24 Jul 2018 12:31:01 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 24 Jul 2018 12:31:01 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w6OHUt8T031458; Tue, 24 Jul 2018 12:30:58 -0500 From: Vignesh R To: Tony Lindgren CC: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , , , , , Vignesh R Subject: [PATCH v3 1/4] dt-bindings: PCI: dra7xx: Add bindings for unaligned access in host mode Date: Tue, 24 Jul 2018 23:01:47 +0530 Message-ID: <20180724173150.2701-2-vigneshr@ti.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180724173150.2701-1-vigneshr@ti.com> References: <20180724173150.2701-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update device tree binding documentation of TI's dra7xx PCI controller for enabling unaligned mem access as applicable not just in EP mode but in host mode as well. Signed-off-by: Vignesh R Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 7f7af3044016..452fe48c4fdd 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -26,6 +26,11 @@ HOST MODE ranges, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. DEVICE MODE =========== -- 2.18.0