From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58197C67790 for ; Fri, 27 Jul 2018 12:05:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1902F208A5 for ; Fri, 27 Jul 2018 12:05:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1902F208A5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730997AbeG0N1X (ORCPT ); Fri, 27 Jul 2018 09:27:23 -0400 Received: from mail.bootlin.com ([62.4.15.54]:35172 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730703AbeG0N1X (ORCPT ); Fri, 27 Jul 2018 09:27:23 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 9CBB020798; Fri, 27 Jul 2018 14:05:44 +0200 (CEST) Received: from localhost (unknown [88.128.81.178]) by mail.bootlin.com (Postfix) with ESMTPSA id 5FB0620717; Fri, 27 Jul 2018 14:05:44 +0200 (CEST) From: Alexandre Belloni To: Mark Brown , James Hogan Cc: Paul Burton , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Thomas Petazzoni , Allan Nielsen , Alexandre Belloni , Rob Herring Subject: [PATCH v2 1/4] dt-bindings: spi: snps,dw-apb-ssi: document Microsemi integration Date: Fri, 27 Jul 2018 14:05:32 +0200 Message-Id: <20180727120535.16504-2-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727120535.16504-1-alexandre.belloni@bootlin.com> References: <20180727120535.16504-1-alexandre.belloni@bootlin.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The integration of the Designware SPI controller on Microsemi SoCs requires an extra register set to be able to give the IP control of the SPI interface. Cc: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 204b311e0400..d97b9fc4c1cb 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -1,8 +1,9 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: -- compatible : "snps,dw-apb-ssi" -- reg : The register base for the controller. +- compatible : "snps,dw-apb-ssi" or "mscc,-spi" +- reg : The register base for the controller. For "mscc,-spi", a second + register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. -- 2.18.0