From: Jacek Tomaka <jacekt@dugeo.com>
To: peterz@infradead.org, linux-kernel@vger.kernel.org,
mingo@redhat.com, tglx@linutronix.de
Cc: Jacek Tomaka <jacek.tomaka@poczta.fm>
Subject: [PATCH v2] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus
Date: Mon, 30 Jul 2018 22:28:13 +0800 [thread overview]
Message-ID: <20180730142813.13451-1-jacekt@dugeo.com> (raw)
From: Jacek Tomaka <jacek.tomaka@poczta.fm>
Problem: perf did not show branch predicted/mispredicted bit in brstack.
Output of perf -F brstack for profile collected
Before:
0x4fdbcd/0x4fdc03/-/-/-/0
0x45f4c1/0x4fdba0/-/-/-/0
0x45f544/0x45f4bb/-/-/-/0
0x45f555/0x45f53c/-/-/-/0
0x7f66901cc24b/0x45f555/-/-/-/0
0x7f66901cc22e/0x7f66901cc23d/-/-/-/0
0x7f66901cc1ff/0x7f66901cc20f/-/-/-/0
0x7f66901cc1e8/0x7f66901cc1fc/-/-/-/0
After:
0x4fdbcd/0x4fdc03/P/-/-/0
0x45f4c1/0x4fdba0/P/-/-/0
0x45f544/0x45f4bb/P/-/-/0
0x45f555/0x45f53c/P/-/-/0
0x7f66901cc24b/0x45f555/P/-/-/0
0x7f66901cc22e/0x7f66901cc23d/P/-/-/0
0x7f66901cc1ff/0x7f66901cc20f/P/-/-/0
0x7f66901cc1e8/0x7f66901cc1fc/P/-/-/0
Cause:
As mentioned in Software Development Manual vol 3, 17.4.8.1,
IA32_PERF_CAPABILITIES[5:0] indicates the format of the address that is
stored in the LBR stack. Knights Landing reports 1 (LBR_FORMAT_LIP) as
its format. Despite that, registers containing FROM address of the branch,
do have MISPREDICT bit but because of the format indicated in
IA32_PERF_CAPABILITIES[5:0], LBR did not read MISPREDICT bit.
Solution:
Teach LBR about above Knights Landing quirk and make it read MISPREDICT bit.
---
arch/x86/events/intel/lbr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cf372b9055..043aa09f3a 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -19,7 +19,7 @@ enum {
LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
};
-static const enum {
+static enum {
LBR_EIP_FLAGS = 1,
LBR_TSX = 2,
} lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
@@ -1230,4 +1230,8 @@ void intel_pmu_lbr_init_knl(void)
x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
x86_pmu.lbr_sel_map = snb_lbr_sel_map;
+
+ /* Knights Landing does have MISPREDICT bit */
+ if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
+ lbr_desc[LBR_FORMAT_LIP] |= LBR_EIP_FLAGS;
}
--
2.17.0
next reply other threads:[~2018-07-30 14:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-30 14:28 Jacek Tomaka [this message]
2018-07-30 16:17 ` Peter Zijlstra
[not found] ` <CAKVxXCVjBaW1kFA48r-bKwrnzR9+SaFXtgaBTb-tr6QHeu1srg@mail.gmail.com>
[not found] ` <CAKVxXCVoRb8Hf18AmUF7RcyNy7JACKByj2FsVOSiO31=ZHFHYQ@mail.gmail.com>
2018-07-30 16:48 ` Peter Zijlstra
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