From: Christoph Hellwig <hch@lst.de>
To: tglx@linutronix.de, palmer@sifive.com, jason@lakedaemon.net,
marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com
Cc: anup@brainfault.org, atish.patra@wdc.com,
devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
shorne@gmail.com
Subject: [PATCH 05/11] RISC-V: simplify software interrupt / IPI code
Date: Thu, 2 Aug 2018 13:50:02 +0200 [thread overview]
Message-ID: <20180802115008.4031-6-hch@lst.de> (raw)
In-Reply-To: <20180802115008.4031-1-hch@lst.de>
Rename handle_ipi to riscv_software_interrupt, drop the unused return
value and move the prototype to irq.h together with riscv_timer_interupt.
This allows simplifying the upcoming interrupt handling support.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/riscv/include/asm/irq.h | 1 +
arch/riscv/include/asm/smp.h | 3 ---
arch/riscv/kernel/smp.c | 6 ++----
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index 4dee9d4c13c0..c871661c9df4 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -22,6 +22,7 @@
#define INTERRUPT_CAUSE_EXTERNAL 9
void riscv_timer_interrupt(void);
+void riscv_software_interrupt(void);
#include <asm-generic/irq.h>
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 85e4220839b0..c9395fff246f 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -44,9 +44,6 @@ void arch_send_call_function_single_ipi(int cpu);
*/
#define raw_smp_processor_id() (*((int*)((char*)get_current() + TASK_TI_CPU)))
-/* Interprocessor interrupt handler */
-irqreturn_t handle_ipi(void);
-
#endif /* CONFIG_SMP */
#endif /* _ASM_RISCV_SMP_H */
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 6d3962435720..906fe21ea21b 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -45,7 +45,7 @@ int setup_profiling_timer(unsigned int multiplier)
return -EINVAL;
}
-irqreturn_t handle_ipi(void)
+void riscv_software_interrupt(void)
{
unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
@@ -60,7 +60,7 @@ irqreturn_t handle_ipi(void)
ops = xchg(pending_ipis, 0);
if (ops == 0)
- return IRQ_HANDLED;
+ return;
if (ops & (1 << IPI_RESCHEDULE))
scheduler_ipi();
@@ -73,8 +73,6 @@ irqreturn_t handle_ipi(void)
/* Order data access and bit testing. */
mb();
}
-
- return IRQ_HANDLED;
}
static void
--
2.18.0
next prev parent reply other threads:[~2018-08-02 11:50 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig
2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig
2018-08-08 14:44 ` Rob Herring
2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig
2018-08-08 14:43 ` Rob Herring
2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 22:08 ` Atish Patra
2018-08-03 13:30 ` Christoph Hellwig
2018-08-06 20:59 ` Rob Herring
2018-08-07 7:20 ` Christoph Hellwig
2018-08-08 2:17 ` Palmer Dabbelt
2018-08-08 6:42 ` Atish Patra
2018-08-08 14:16 ` Rob Herring
2018-08-08 15:09 ` Christoph Hellwig
2018-08-08 16:47 ` Marc Zyngier
2018-08-08 16:57 ` Christoph Hellwig
2018-08-09 10:19 ` Marc Zyngier
2018-08-08 19:38 ` Palmer Dabbelt
2018-08-08 23:32 ` Rob Herring
2018-08-09 6:29 ` Palmer Dabbelt
2018-08-09 6:43 ` Christoph Hellwig
2018-08-10 16:57 ` Rob Herring
2018-08-10 20:09 ` Palmer Dabbelt
2018-08-13 14:09 ` Rob Herring
2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-02 11:50 ` Christoph Hellwig [this message]
2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-08-02 22:19 ` Atish Patra
2018-08-03 12:33 ` Christoph Hellwig
2018-08-04 9:58 ` Christoph Hellwig
2018-08-06 20:34 ` Palmer Dabbelt
2018-08-08 6:47 ` Atish Patra
2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-02 23:13 ` Atish Patra
2018-08-03 12:29 ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-02 23:21 ` Atish Patra
2018-08-03 12:31 ` Christoph Hellwig
2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt
2018-08-03 7:49 ` Thomas Gleixner
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