From: Christoph Hellwig <hch@lst.de>
To: tglx@linutronix.de, palmer@sifive.com, jason@lakedaemon.net,
marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com
Cc: anup@brainfault.org, atish.patra@wdc.com,
devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
shorne@gmail.com
Subject: simplified RISC-V interrupt and clocksource handling v3
Date: Sat, 4 Aug 2018 10:23:11 +0200 [thread overview]
Message-ID: <20180804082319.5711-1-hch@lst.de> (raw)
This series tries adds support for interrupt handling and timers
for the RISC-V architecture.
The basic per-hart interrupt handling implemented by the scause
and sie CSRs is extremely simple and implemented directly in
arch/riscv/kernel/irq.c. In addition there is a irqchip driver
for the PLIC external interrupt controller, which is called through
the set_handle_irq API, and a clocksource driver that gets its
timer interrupt directly from the low-level interrupt handling.
Compared to previous iterations this version does not try to use an
irqchip driver for the low-level interrupt handling. This saves
a couple indirect calls and an additional read of the scause CSR
in the hot path, makes the code much simpler and last but not least
avoid the dependency on a device tree for a mandatory architectural
feature.
A git tree is available here (contains a few more patches before
the ones in this series)
git://git.infradead.org/users/hch/riscv.git riscv-irq-simple.3
Gitweb:
http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-irq-simple.3
Changes since v2:
- actually use SEIE instead of STIE in the plic driver
- rename the default compat string for the plic to sifive,u5-plic
- various spelling fixes
- drop a superflous derefence in the plic driver that is taken care of
by the following loop
- drop the patch to document the enable method - not relevant for the
rest of the series
- drop the patches for the per-hart timebase frequency - not relevant
for the rest of the series.
- use riscv_of_processor_hart in the timer driver
Changes since v1:
- rename the plic driver to irq-sifive-plic
- switch to a default compatible of sifive,plic0 (still supporting the
riscv,plic0 name for compatibility)
- add a reference for the SiFive PLIC register layout
- fix plic_toggle addressing for large numbers of hwirqs
- remove the call to ack_bad_irq
- use a raw spinlock for plic_toggle_lock
- use the irq_desc cpumask in the plic enable/disable methods
- add back OF contexid parsing in the plic driver
- don't allow COMPILE_TEST builds of the clocksource driver, as it
depends on <asm/sbi.h>
- default the clocksource driver to y
- clean up naming in the clocksource driver
- remove the MINDELTA and MAXDELTA #defines
- various DT binding fixes
next reply other threads:[~2018-08-04 8:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-04 8:23 Christoph Hellwig [this message]
2018-08-04 8:23 ` [PATCH 1/8] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-04 8:23 ` [PATCH 2/8] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-04 8:23 ` [PATCH 3/8] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-04 8:23 ` [PATCH 4/8] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-04 8:23 ` [PATCH 5/8] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-04 8:23 ` [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-08 14:29 ` Rob Herring
2018-08-08 15:04 ` Christoph Hellwig
2018-08-08 16:15 ` Rob Herring
2018-08-08 16:41 ` Christoph Hellwig
2018-08-08 20:49 ` Palmer Dabbelt
2018-08-04 8:23 ` [PATCH 7/8] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-06 20:27 ` Atish Patra
2018-08-04 8:23 ` [PATCH 8/8] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-08 2:23 ` simplified RISC-V interrupt and clocksource handling v3 Palmer Dabbelt
2018-08-08 6:27 ` Christoph Hellwig
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