From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 243E5C46464 for ; Thu, 9 Aug 2018 07:08:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D262E21B31 for ; Thu, 9 Aug 2018 07:08:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D262E21B31 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728142AbeHIJbw (ORCPT ); Thu, 9 Aug 2018 05:31:52 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:46844 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727525AbeHIJbw (ORCPT ); Thu, 9 Aug 2018 05:31:52 -0400 Received: from ofmlt.linux-actions.org (10.18.20.235) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 9 Aug 2018 15:08:26 +0800 From: Yixun Lan To: Jerome Brunet , Neil Armstrong CC: Yixun Lan , Kevin Hilman , Carlo Caione , Rob Herring , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , , , , , Subject: [PATCH v4 0/3] clk: meson: add a sub EMMC clock controller support Date: Thu, 9 Aug 2018 15:07:20 +0800 Message-ID: <20180809070724.11935-1-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.20.235] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun.lan@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun.lan@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun.lan@amlogic.com Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver .../bindings/clock/amlogic,mmc-clkc.txt | 31 ++ drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-phase-delay.c | 96 ++++++ drivers/clk/meson/clkc.h | 13 + drivers/clk/meson/mmc-clkc.c | 275 ++++++++++++++++++ include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 7 files changed, 444 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 2.17.1