From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5EE6C6778D for ; Tue, 11 Sep 2018 08:22:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 60F0A20854 for ; Tue, 11 Sep 2018 08:22:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 60F0A20854 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727007AbeIKNVD (ORCPT ); Tue, 11 Sep 2018 09:21:03 -0400 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:28336 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726645AbeIKNVD (ORCPT ); Tue, 11 Sep 2018 09:21:03 -0400 X-IronPort-AV: E=Sophos;i="5.53,359,1531810800"; d="scan'208";a="19722861" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 11 Sep 2018 01:22:50 -0700 Received: from localhost.localdomain.com (10.10.76.4) by chn-sv-exch07.mchp-main.com (10.10.76.108) with Microsoft SMTP Server id 14.3.352.0; Tue, 11 Sep 2018 01:22:50 -0700 From: Tudor Ambarus To: , , , , , , , , , , CC: Tudor Ambarus Subject: [PATCH v2 3/3] mtd: spi-nor: add support for Microchip SST26 QSPI flash memories Date: Tue, 11 Sep 2018 11:22:32 +0300 Message-ID: <20180911082232.28678-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20180911082232.28678-1-tudor.ambarus@microchip.com> References: <20180911082232.28678-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The flash memories are write-protected by default at power-on and must be unlocked first, before being erased, then programmed. The erase block sizes are not uniform. The memory layout is uniform just for the 4K sector blocks. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ba0fd8b..dc8757e 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1164,10 +1164,30 @@ static const struct flash_info spi_nor_ids[] = { { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, { + "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + UNLOCK_GLOBAL_BLOCK) + }, + { + "sst26vf032b", INFO(0xbf2642, 0, 64 * 1024, 64, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + UNLOCK_GLOBAL_BLOCK) + }, + { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | UNLOCK_GLOBAL_BLOCK) }, + { + "sst26vf040b", INFO(0xbf2654, 0, 64 * 1024, 8, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + UNLOCK_GLOBAL_BLOCK) + }, + { + "sst26vf080b", INFO(0xbf2658, 0, 64 * 1024, 16, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + UNLOCK_GLOBAL_BLOCK) + }, /* ST Microelectronics -- newer production may have feature updates */ { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, -- 2.9.4