From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7ADBC433F4 for ; Fri, 21 Sep 2018 03:29:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B39021533 for ; Fri, 21 Sep 2018 03:29:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B39021533 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389247AbeIUJPu (ORCPT ); Fri, 21 Sep 2018 05:15:50 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:15649 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389091AbeIUJP2 (ORCPT ); Fri, 21 Sep 2018 05:15:28 -0400 X-UUID: b28d8c4fd5304236b191155e83d16df7-20180921 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 860154289; Fri, 21 Sep 2018 11:28:33 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Sep 2018 11:28:26 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Sep 2018 11:28:26 +0800 From: Bibby Hsieh To: David Airlie , Matthias Brugger , Daniel Vetter , , CC: Yingjoe Chen , Cawa Cheng , Daniel Kurtz , Bibby Hsieh , Philipp Zabel , YT Shen , Thierry Reding , CK Hu , Mao Huang , , , Sascha Hauer , chunhui dai Subject: [PATCH v3 04/12] drm/mediatek: add clock factor for different IC Date: Fri, 21 Sep 2018 11:28:14 +0800 Message-ID: <20180921032822.30771-5-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.12.5.2.gbdf23ab In-Reply-To: <20180921032822.30771-1-bibby.hsieh@mediatek.com> References: <20180921032822.30771-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: A345D91ACD21587670C94CD62DD174317C3473260263CE050BD97B452B02155F2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: chunhui dai different IC has different clock designed in HDMI, the factor for calculate clock should be different. Usinng the data in of_node to find this factor. Signed-off-by: chunhui dai --- drivers/gpu/drm/mediatek/mtk_dpi.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 1e7369e0d91c..022ccec49cea 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { }; struct mtk_dpi_conf { + unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; bool edge_sel_en; }; @@ -460,15 +461,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, unsigned int factor; /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ - - if (mode->clock <= 27000) - factor = 3 << 4; - else if (mode->clock <= 84000) - factor = 3 << 3; - else if (mode->clock <= 167000) - factor = 3 << 2; - else - factor = 3 << 1; + factor = dpi->conf->cal_factor(mode->clock); drm_display_mode_to_videomode(mode, &vm); pll_rate = vm.pixelclock * factor; @@ -682,7 +675,20 @@ static const struct component_ops mtk_dpi_component_ops = { .unbind = mtk_dpi_unbind, }; +static unsigned int mt8173_calculate_factor(int clock) +{ + if (clock <= 27000) + return 3 << 4; + else if (clock <= 84000) + return 3 << 3; + else if (clock <= 167000) + return 3 << 2; + else + return 3 << 1; +} + static const struct mtk_dpi_conf mt8173_conf = { + .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, }; -- 2.12.5.2.gbdf23ab