From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D567C43382 for ; Thu, 27 Sep 2018 14:00:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD5DA216FA for ; Thu, 27 Sep 2018 14:00:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AD5DA216FA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=renesas.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727692AbeI0US3 (ORCPT ); Thu, 27 Sep 2018 16:18:29 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:50005 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727240AbeI0US2 (ORCPT ); Thu, 27 Sep 2018 16:18:28 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 27 Sep 2018 23:00:03 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 9E82E8A860; Thu, 27 Sep 2018 23:00:03 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.54,310,1534777200"; d="scan'208";a="292093595" Received: from unknown (HELO vbox.ree.adwin.renesas.com) ([10.226.37.67]) by relmlii1.idc.renesas.com with ESMTP; 27 Sep 2018 22:59:59 +0900 From: Phil Edworthy To: Geert Uytterhoeven , Laurent Pinchart Cc: Jacopo Mondi , Linus Walleij , Simon Horman , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Phil Edworthy Subject: [PATCH v6 3/3] ARM: dts: r9a06g032: Add pinctrl node Date: Thu, 27 Sep 2018 14:59:22 +0100 Message-Id: <20180927135922.12015-4-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927135922.12015-1-phil.edworthy@renesas.com> References: <20180927135922.12015-1-phil.edworthy@renesas.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This provides a pinctrl driver for the Renesas R9A06G032 SoC Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy --- v6: - No changes. v5: - No changes. v4: - No changes. v3: - No changes. v2: - Add "renesas,rzn1-pinctrl" compatible fallback string - Register size corrected. --- arch/arm/boot/dts/r9a06g032.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index eaf94976ed6d..2322268bc862 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -165,6 +165,14 @@ status = "disabled"; }; + pinctrl: pin-controller@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + status = "okay"; + }; + gic: gic@44101000 { compatible = "arm,cortex-a7-gic", "arm,gic-400"; interrupt-controller; -- 2.17.1