From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 838E3C43382 for ; Fri, 28 Sep 2018 12:19:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 38C282159D for ; Fri, 28 Sep 2018 12:19:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 38C282159D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728879AbeI1Smi (ORCPT ); Fri, 28 Sep 2018 14:42:38 -0400 Received: from foss.arm.com ([217.140.101.70]:48430 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726068AbeI1Smi (ORCPT ); Fri, 28 Sep 2018 14:42:38 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F812ED1; Fri, 28 Sep 2018 05:19:07 -0700 (PDT) Received: from brain-police (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EEB783F5D3; Fri, 28 Sep 2018 05:19:04 -0700 (PDT) Date: Fri, 28 Sep 2018 13:19:01 +0100 From: Will Deacon To: Robin Murphy Cc: joro@8bytes.org, thunder.leizhen@huawei.com, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linuxarm@huawei.com, guohanjun@huawei.com, huawei.libin@huawei.com, john.garry@huawei.com Subject: Re: [PATCH v8 5/7] iommu/arm-smmu-v3: Add support for non-strict mode Message-ID: <20180928121900.GB1577@brain-police> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 20, 2018 at 05:10:25PM +0100, Robin Murphy wrote: > From: Zhen Lei > > Now that io-pgtable knows how to dodge strict TLB maintenance, all > that's left to do is bridge the gap between the IOMMU core requesting > DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE for default domains, and showing the > appropriate IO_PGTABLE_QUIRK_NON_STRICT flag to alloc_io_pgtable_ops(). > > Signed-off-by: Zhen Lei > [rm: convert to domain attribute, tweak commit message] > Signed-off-by: Robin Murphy > --- > > v8: > - Use nested switches for attrs > - Document barrier semantics > > drivers/iommu/arm-smmu-v3.c | 79 ++++++++++++++++++++++++++----------- > 1 file changed, 56 insertions(+), 23 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index f10c852479fc..db402e8b068b 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -612,6 +612,7 @@ struct arm_smmu_domain { > struct mutex init_mutex; /* Protects smmu pointer */ > > struct io_pgtable_ops *pgtbl_ops; > + bool non_strict; > > enum arm_smmu_domain_stage stage; > union { > @@ -1407,6 +1408,12 @@ static void arm_smmu_tlb_inv_context(void *cookie) > cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; > } > > + /* > + * NOTE: when io-pgtable is in non-strict mode, we may get here with > + * PTEs previously cleared by unmaps on the current CPU not yet visible > + * to the SMMU. We are relying on the DSB implicit in queue_inc_prod() > + * to guarantee those are observed before the TLBI. Do be careful, 007. > + */ Good, so you can ignore my comment on the previous patch :) Will