From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, mark.rutland@arm.com, pelcan@codeaurora.org,
shankerd@codeaurora.org, suzuki.poulose@arm.com
Subject: [PATCH v2 0/3] arm64: cpufeature: Fix handling of CTR_EL0
Date: Tue, 9 Oct 2018 14:47:04 +0100 [thread overview]
Message-ID: <20181009134707.3479-2-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20181009134707.3479-1-suzuki.poulose@arm.com>
This series makes sure that we handle the CTR_EL0 field mismatches
properly, especially for the IDC field. Also, skip trapping CTR
accesses on a CPU if it matches the safe value.
Applies on arm64 for-next/core.
Changes since v1
- Fix wrong hunk in has_cache_idc()
- Allow a late secondary CPU with raw CTR_EL0.IDC = 0 and effective
CTR_EL0.IDC = 1, to boot on a system without IDC available.
Suzuki K Poulose (3):
arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
arm64: cpufeature: Fix handling of CTR_EL0.IDC field
arm64: cpufeature: Trap CTR_EL0 access only where it is necessary
arch/arm64/include/asm/cache.h | 40 ++++++++++++++++++++++++++++++++++
arch/arm64/kernel/cpu_errata.c | 34 +++++++++++++++++++++++++----
arch/arm64/kernel/cpufeature.c | 35 +++++++++++++++++++++++++----
arch/arm64/kernel/cpuinfo.c | 10 ++++++++-
4 files changed, 110 insertions(+), 9 deletions(-)
--
2.19.0
next prev parent reply other threads:[~2018-10-09 13:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-09 13:47 Suzuki K Poulose
2018-10-09 13:47 ` Suzuki K Poulose [this message]
2018-10-09 13:47 ` [PATCH v2 1/3] arm64: cpufeature: ctr: Fix cpu capability check for late CPUs Suzuki K Poulose
2018-10-09 13:47 ` [PATCH v2 2/3] arm64: cpufeature: Fix handling of CTR_EL0.IDC field Suzuki K Poulose
2018-10-09 13:47 ` [PATCH v2 3/3] arm64: cpufeature: Trap CTR_EL0 access only where it is necessary Suzuki K Poulose
2018-10-16 11:00 ` [PATCH v2 0/3] arm64: cpufeature: Fix handling of CTR_EL0 Catalin Marinas
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