From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15910C04AA5 for ; Mon, 15 Oct 2018 17:21:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D8D592064A for ; Mon, 15 Oct 2018 17:21:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D8D592064A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726906AbeJPBIA (ORCPT ); Mon, 15 Oct 2018 21:08:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:47640 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726638AbeJPBIA (ORCPT ); Mon, 15 Oct 2018 21:08:00 -0400 Received: from brain-police (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C7C63208E4; Mon, 15 Oct 2018 17:21:49 +0000 (UTC) Date: Mon, 15 Oct 2018 18:21:46 +0100 From: Will Deacon To: Zhen Lei Cc: Robin Murphy , Joerg Roedel , linux-arm-kernel , iommu , linux-kernel , LinuxArm Subject: Re: [PATCH 1/1] iommu/arm-smmu-v3: eliminate a potential memory corruption on Hi16xx soc Message-ID: <20181015172146.GD31305@brain-police> References: <1539592576-24352-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1539592576-24352-1-git-send-email-thunder.leizhen@huawei.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote: > ITS translation register map: > 0x0000-0x003C Reserved > 0x0040 GITS_TRANSLATER > 0x0044-0xFFFC Reserved > > The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon > expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes > data will be written to MSIAddress each time. > > MSIAddr: |----4bytes----|----4bytes----| > | MSIData | IMPDEF | > > There is no problem for ITS, because the next 4 bytes space is reserved in ITS. > But it will overwrite the 4 bytes memory following "sync_count". It's very > luckly that the previous and the next neighbour of "sync_count" are both aligned > by 8 bytes, so no problem is met now. > > It's good to explicitly add a workaround: > 1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always > aligned by 8 bytes. > 2. Add a "u64" union member to make sure the 4 bytes padding is always exist. > > There is no functional change. > > Signed-off-by: Zhen Lei > --- > drivers/iommu/arm-smmu-v3.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index 5059d09..a07bc0d 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -586,7 +586,10 @@ struct arm_smmu_device { > > struct arm_smmu_strtab_cfg strtab_cfg; > > + union { > + u64 padding; /* workaround for Hisilicon */ > u32 sync_count; > + } __attribute__((aligned(8))); Won't this already be aligned by the ABI? Anyway, you'll need to swizzle things for big-endian, I suspect. Maybe you can do something clever like making sync_count an array of two elements and determining the offset based on the endianness. Or just keep it simple like we do for things like struct qrwlock and struct qspinlock and use #ifdefs. Also -- you need a comment to explain this insanity :) Will