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[2003:dc:d717:a100:6d21:4a3b:238:44e6]) by smtp.googlemail.com with ESMTPSA id z192-v6sm16610273wmc.37.2018.11.16.12.53.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 12:53:32 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 0/3] Meson8b: add the CPU clock post-dividers Date: Fri, 16 Nov 2018 21:53:00 +0100 Message-Id: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is the successor to my previous series "meson8b: add the CPU_DIV16 clock for the ARM TWD" from [0]. I decided to not send this as v2 of the original series because the PERIPH clock is not the CPU_DIV16 clock. It's not clear whether a CPU_DIV16 clock exists. With this series we get all the CPU_CLK post-dividers as listed in the public S805 datasheet [1] on pages 31 and 32: - ABP - PERIPH (used as input for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Each of these clocks has a register called "..._CLK_DIS" which is documented as a "just in case" bit: "Set to 1 to manually disable the [...] clock when changing the mux selection. Typically this bit is set to 0 since the clock muxes can switch without glitches." Since we're not supposed to touch that register we're setting CLK_IS_CRITICAL for these clocks in the driver. The result of this is that we can use the PERIPH clock which clocks the ARM TWD timer. I will send a separate series to add the TWD timer. [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html [1] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf Martin Blumenstingl (3): dt-bindings: clock: meson8b: export the CPU post dividers clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: meson8b: add the CPU clock post divider clocks drivers/clk/meson/meson8b.c | 268 ++++++++++++++++++++++- drivers/clk/meson/meson8b.h | 17 +- include/dt-bindings/clock/meson8b-clkc.h | 4 + 3 files changed, 276 insertions(+), 13 deletions(-) -- 2.19.1