Re: [PATCH] USB: host: ehci: allow tine of highspeed nak-count

[Ben Dooks <ben@fluff.org>]

On Fri, Nov 16, 2018 at 10:38:18AM -0500, Alan Stern wrote:
> On Fri, 16 Nov 2018, Ben Dooks wrote:
> 
> > On 14/11/18 18:47, Alan Stern wrote:
> > > On Wed, 14 Nov 2018, Ben Dooks wrote:
> > > 
> > >> From: Ben Dooks <ben.dooks@codethink.co.uk>
> > >>
> > >> At least some systems benefit with less scheduling if the NAK count
> > >> value is set higher than the default 4. For instance a Tegra3 with
> > >> an SMSC9512 showed less interrupt load when this was changed to 14.
> > > 
> > > Interesting.  Why do you think this is?  In theory, increasing the NAK
> > > count RL value should cause a higher memory bus load and perhaps a
> > > slight rise in the interrupt load (transfers will complete a little
> > > more quickly because the controller tries harder to poll the endpoints
> > > and see if they are ready).
> > 
> > I thought the NAK counter was decremented until the transfer is given
> > up on.
> 
> That's right.  So if the RL value is higher, there will be more polling
> attempts in quick succession before the NAK counter drops to 0 and the
> controller gives up.  More polling attempts in quick succession means 
> heavier memory bus usage.
> 
> > I'm going to have to go back and get some actual figures from
> > a running system as this was originally done over a year ago with the
> > SMSC9512 (IIRC) network driver.
> > 
> > >> To allow the changing of this value, add a sysfs node to each of
> > >> the controllers to allow run-time changing.
> > >>
> > >> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> > > 
> > > The patch looks okay to me.
> > 
> > I'll look at getting some tracing from the SMSC driver to see what
> > is going on.
> 
> Okay.  Should we consider the patch to be held in suspense until then?

Yes, I'm not going to have access to any of the test hardware until the
end of the week, and will re-verify my initial notes from last year.

-- 
Ben Dooks, ben@fluff.org, http://www.fluff.org/ben/

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