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[158.174.22.210]) by smtp.gmail.com with ESMTPSA id j76-v6sm393983ljb.12.2018.11.29.09.47.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 09:47:56 -0800 (PST) From: Ulf Hansson To: "Rafael J . Wysocki" , Sudeep Holla , Lorenzo Pieralisi , Mark Rutland , Daniel Lezcano , linux-pm@vger.kernel.org Cc: "Raju P . L . S . S . S . N" , Stephen Boyd , Tony Lindgren , Kevin Hilman , Lina Iyer , Ulf Hansson , Viresh Kumar , Vincent Guittot , Geert Uytterhoeven , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 27/27] arm64: dts: hikey: Convert to the hierarchical CPU topology layout Date: Thu, 29 Nov 2018 18:47:00 +0100 Message-Id: <20181129174700.16585-28-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181129174700.16585-1-ulf.hansson@linaro.org> References: <20181129174700.16585-1-ulf.hansson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To enable the OS to manage last-man standing activities for a CPU, while an idle state for a group of CPUs is selected, let's convert the Hikey platform into using the hierarchical CPU topology layout. Signed-off-by: Ulf Hansson --- Changes in v10: - New patch. --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 87 ++++++++++++++++++++--- 1 file changed, 76 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 97d5bf2c6ec5..fa5b385cfbc4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -20,6 +20,64 @@ psci { compatible = "arm,psci-0.2"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CLUSTER_PD0: cluster-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; + + CLUSTER_PD1: cluster-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; }; cpus { @@ -70,9 +128,8 @@ }; CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000000>; entry-latency-us = <1000>; exit-latency-us = <700>; min-residency-us = <2700>; @@ -88,9 +145,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; cpu1: cpu@1 { @@ -101,9 +159,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; cpu2: cpu@2 { @@ -114,9 +173,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; cpu3: cpu@3 { @@ -127,9 +187,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; cpu4: cpu@100 { @@ -140,9 +201,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; }; cpu5: cpu@101 { @@ -153,9 +215,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; }; cpu6: cpu@102 { @@ -166,9 +229,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; }; cpu7: cpu@103 { @@ -179,9 +243,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; }; CLUSTER0_L2: l2-cache0 { -- 2.17.1