From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01BE0C64EB4 for ; Fri, 30 Nov 2018 08:02:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B0A132082F for ; Fri, 30 Nov 2018 08:02:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="pX7HPyIt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0A132082F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727071AbeK3TKs (ORCPT ); Fri, 30 Nov 2018 14:10:48 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:38730 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726589AbeK3TKs (ORCPT ); Fri, 30 Nov 2018 14:10:48 -0500 Received: by mail-pg1-f193.google.com with SMTP id g189so2159722pgc.5 for ; Fri, 30 Nov 2018 00:02:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EWRMoEC/A0hBjLIZuy6KvNFGbEVqYyO/63HQJNeKmb0=; b=pX7HPyItHcvL7I8CcRC8mkwocrohyKK3alsWU9f5QyEhzn++uVl2rDF8JQpfm9Po0F RvisQ3PFP1wqGQSwcjnV8tCuC3mKVA9uMu8uWXVQBOn21iGnQ8Allzn8AQe2lHbp/62e feBUxcOG3gAN7bZ4qWxb16X3INMEg+S+2RUADXLR6M6nN/F2ynYc72Uq72DIH7DDgyjv ASJvyiIuzTZElpns+FNBtnwsOtszMI5AXDpxEs+QfpA5Wb08QOwPde2AQiT+KF4dWlP3 EcvsbREhGyd1RmsMANr3kyMngc7xJ+HG1y0kgCuBZCRzB9vfKKRVIg5KrgaCQhPfbI/d 9MuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EWRMoEC/A0hBjLIZuy6KvNFGbEVqYyO/63HQJNeKmb0=; b=YnXalxnlKvXFe1f8mWekOzrzipjjhADD61dSCLI8vP428AkGUuwRcuIOfxrXh2JKBP Mjv8vEhrXITJtYoLIyAXQnZckUulV/+k1Fg+62ZMWFjwOc4TVjEEbkOEnEtHLhs/w4by H6X8ycgHUm/4OlADR6K/Wu+pbk6KCFKd3QKiTNjoFQQps2tUA1HHwq+hq3vVKIdpO0ow zYliuA52aHnIhSD1+5Fa4U2dBo1SLTns86l8d3lQKUtoLKKbJJWkdNtsgHnXAO55BE1n ya7gdi5SdR3I2S/WzcY4clDujQihVJFfPTpCMm9jve3GqDH5ROS1X+T+RCMz8q9p6H/2 OZow== X-Gm-Message-State: AA+aEWZJRVoxrFocqMfgagC1puFAp1g5q952fUxRoMJnGXUzFGVRNzs7 3PKs+kNd+HIpf/HlAStZuFOxJg== X-Google-Smtp-Source: AFSGD/Ub6+Gy2QjoIjZVBIMAwBrw3VEeQrDAKyz5rAgWqgdnxHYwwjZIs/V44sgepk1OjgJblvIjpw== X-Received: by 2002:a62:2f06:: with SMTP id v6mr4722584pfv.216.1543564940610; Fri, 30 Nov 2018 00:02:20 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.52.208]) by smtp.googlemail.com with ESMTPSA id q187sm19218333pfq.128.2018.11.30.00.02.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 00:02:19 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Atish Patra , Christoph Hellwig , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base Date: Fri, 30 Nov 2018 13:32:02 +0530 Message-Id: <20181130080207.20505-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181130080207.20505-1-anup@brainfault.org> References: <20181130080207.20505-1-anup@brainfault.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 47 ++++++++++++++----------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 357e9daf94ae..c23a293a2aae 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -59,37 +59,28 @@ static void __iomem *plic_regs; struct plic_handler { bool present; - int ctxid; + void __iomem *hart_base; + /* + * Protect mask operations on the registers given that we can't + * assume atomic memory operations work on them. + */ + raw_spinlock_t enable_lock; + void __iomem *enable_base; }; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); -static inline void __iomem *plic_hart_offset(int ctxid) -{ - return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART; -} - -static inline u32 __iomem *plic_enable_base(int ctxid) -{ - return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART; -} - -/* - * Protect mask operations on the registers given that we can't assume that - * atomic memory operations work on them. - */ -static DEFINE_RAW_SPINLOCK(plic_toggle_lock); - -static inline void plic_toggle(int ctxid, int hwirq, int enable) +static inline void plic_toggle(struct plic_handler *handler, + int hwirq, int enable) { - u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32); + u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); u32 hwirq_mask = 1 << (hwirq % 32); - raw_spin_lock(&plic_toggle_lock); + raw_spin_lock(&handler->enable_lock); if (enable) writel(readl(reg) | hwirq_mask, reg); else writel(readl(reg) & ~hwirq_mask, reg); - raw_spin_unlock(&plic_toggle_lock); + raw_spin_unlock(&handler->enable_lock); } static inline void plic_irq_toggle(struct irq_data *d, int enable) @@ -101,7 +92,7 @@ static inline void plic_irq_toggle(struct irq_data *d, int enable) struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); if (handler->present) - plic_toggle(handler->ctxid, d->hwirq, enable); + plic_toggle(handler, d->hwirq, enable); } } @@ -150,7 +141,7 @@ static struct irq_domain *plic_irqdomain; static void plic_handle_irq(struct pt_regs *regs) { struct plic_handler *handler = this_cpu_ptr(&plic_handlers); - void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM; + void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; irq_hw_number_t hwirq; WARN_ON_ONCE(!handler->present); @@ -239,12 +230,16 @@ static int __init plic_init(struct device_node *node, cpu = riscv_hartid_to_cpuid(hartid); handler = per_cpu_ptr(&plic_handlers, cpu); handler->present = true; - handler->ctxid = i; + handler->hart_base = + plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART; + raw_spin_lock_init(&handler->enable_lock); + handler->enable_base = + plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; /* priority must be > threshold to trigger an interrupt */ - writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD); + writel(0, handler->hart_base + CONTEXT_THRESHOLD); for (hwirq = 1; hwirq <= nr_irqs; hwirq++) - plic_toggle(i, hwirq, 0); + plic_toggle(handler, hwirq, 0); nr_mapped++; } -- 2.17.1