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[2003:dc:d73f:ba00:b1cc:eb3:8cd2:a4e]) by smtp.googlemail.com with ESMTPSA id a18sm13073110wrp.13.2018.12.02.13.42.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 13:42:38 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, Martin Blumenstingl Subject: [PATCH 2/3] clk: meson: meson8b: add the fractional divider for vid_pll_dco Date: Sun, 2 Dec 2018 22:42:19 +0100 Message-Id: <20181202214220.7715-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181202214220.7715-1-martin.blumenstingl@googlemail.com> References: <20181202214220.7715-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This "vid_pll_dco" (which should be named HDMI_PLL or - as the datasheet calls it - HPLL) has a 12-bit wide fractional parameter at HHI_VID_PLL_CNTL2[11:0]. Add this so we correctly calculate the rate of this PLL when u-boot is configured for a video mode which uses this fractional parameter. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 5 +++++ drivers/clk/meson/meson8b.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a4ae9c957fde..0f3f4759fc92 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -137,6 +137,11 @@ static struct clk_regmap meson8b_vid_pll_dco = { .shift = 10, .width = 5, }, + .frac = { + .reg_off = HHI_VID_PLL_CNTL2, + .shift = 0, + .width = 12, + }, .l = { .reg_off = HHI_VID_PLL_CNTL, .shift = 31, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 0abb331162ab..e953923792d7 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -33,6 +33,7 @@ #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ /* * MPLL register offeset taken from the S905 datasheet. Vendor kernel source -- 2.19.2